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Home/Authors/Jiajun Hu

Jiajun Hu

2 indexed papers

Recent (6 mo)
2
With code
0
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0
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Publications per year

2
26

Top categories

Distributed×1Performance×1Architecture×1

Frequent co-authors

Jiajun Huang1×
Ruthwik Reddy Sunketa1×
Andrew Boutros1×
Aman Arora1×

Research Timeline

2026
Boosting FPGA Performance with Direct BRAM-DSP Paths

This paper proposes a lightweight architectural enhancement for FPGA designs to improve data movement between block RAMs and digital signal processing units for deep learning workloads, incurring negligible area and delay overhead.

FSZ: Breaking the Prediction-Throughput Trade-off in GPU Lossy Compression

This paper proposes FSZ, a GPU error-bounded lossy compressor with three innovations for higher compression ratios and throughput within a single CUDA kernel.

Highlighted terms show continued research focus across papers

Papers

cs.DCcs.PFEmpiricalRecentJul 16, 2026

FSZ: Breaking the Prediction-Throughput Trade-off in GPU Lossy Compression

Jiajun Huang

This paper proposes FSZ, a GPU error-bounded lossy compressor with three innovations for higher compression ratios and throughput within a single CUDA kernel.

View →
cs.AREmpiricalRecent
Jul 7, 2026

Boosting FPGA Performance with Direct BRAM-DSP Paths

Jiajun Hu, Ruthwik Reddy Sunketa, Andrew Boutros, Aman Arora

This paper proposes a lightweight architectural enhancement for FPGA designs to improve data movement between block RAMs and digital signal processing units for deep learning workloads, incurring negl…

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