ZKPU: Zero-Knowledge Processing Unit for Heterogeneous Workloads
This paper presents a Zero-Knowledge Processing Unit (ZKPU) that accelerates zero-knowledge proofs for both curve-based and hash-based protocols.
This paper is the first to provide a unified architecture for both curve-based and hash-based protocols on a single reconfigurable hardware platform.
Before reading this…
Applications
- →Privacy-preserving computation
- →Blockchain systems
- →Verifiable machine learning
To understand this paper, make sure you know these concepts first:
- Zero-knowledge proofsfind papers →
- Reconfigurable architecturefind papers →
Abstract
More Like ThisZero-knowledge proofs (ZKPs) have become a fundamental building block for privacy-preserving computation, blockchain systems, and verifiable machine learning. Modern ZKP protocols span two distinct families: curve-based protocols, which rely on large finite-field arithmetic, and hash-based protocols, which operate over native 64-bit fields. Existing hardware accelerators are specialized for one protocol family because they are built on operand-scanning Montgomery multiplication, resulting in fixed-width datapaths, poor utilization across heterogeneous operand widths, and limited scalability. This paper presents \emph{ZKPU}, a Zero-Knowledge Processing Unit for heterogeneous ZKP workloads. ZKPU introduces a new compute paradigm by co-designing finely integrated product scanning (FIPS) Montgomery multiplication with a reconfigurable Twin Systolic Fabric (TSF), enabling modular multiplication at arbitrary widths in 64-bit increments. Combined with a fine-grained Deque buffer, on-chip twiddle-factor generator, and memory-efficient MSM preprocessing strategy, ZKPU provides a unified architecture for both curve-based and hash-based protocols. Evaluation using Groth16 and Plonky2 shows that ZKPU achieves up to $144\times$ speedup for NTT, $13.6\times$ for MSM, and approximately $7.2\times$ end-to-end application speedup over state-of-the-art accelerators, while being the first architecture to efficiently support both protocol families on a single reconfigurable hardware platform.