The paper establishes a systematic, non-destructive methodology for acquiring and validating ground-truth firmware images from low-cost consumer drones, revealing the presence of vulnerable, unhardene…

The paper introduces Platum, a novel framework that synthesizes verified, low-latency runtime monitors for MAVLink protocols, enabling robust enforcement of contextual message validity on resource-con…

This paper investigates the vulnerability of machine learning-based fault detection and localization systems in Cyber-Physical Systems (CPS) to backdoor attacks, demonstrating that such attacks are su…

The paper introduces HarmChip, a novel benchmark to evaluate LLM vulnerability to domain-specific hardware security threats, revealing that current safety guardrails fail against semantically disguise…

This survey reviews the integration of AI and LLMs into hardware security verification, demonstrating its potential to automate complex stages while stressing the necessity of grounding AI outputs in…

This review analyzes the dual impact of integrating Large Language Models (LLMs) into hardware design, detailing both their transformative potential in EDA and the critical security vulnerabilities th…

Assertain is an automated framework that uses large language models and design analysis to generate high-quality, executable security assertions for hardware designs, significantly outperforming state…

The paper develops a unified mathematical framework to analyze the interaction between post-quantum security, real-time communication constraints, and closed-loop stability in safety-critical turbofan…

The paper proposes a novel hardware extension that enables deterministic, kernel-bypass switching to user-level protection domains upon interrupt arrival, significantly reducing worst-case latency for…

The paper introduces a threat-oriented digital twinning methodology to enable reproducible and controllable cybersecurity evaluation of autonomous platforms, overcoming limitations in accessing real-w…

The paper proposes a proactive, resilient architecture for autonomous vehicles by integrating redundancy, diversity, and adaptive reconfiguration to defend against various cyber and physical attacks.

This paper surveys the use of hardware emulation for security verification in System-on-Chip (SoC) design, positioning emulation as a critical, high-fidelity pre-silicon assurance technology.

This paper experimentally demonstrates that IEC 61850 Sampled Values-based protection systems are vulnerable to stealthy, coordinated False Data Injection Attacks (FDIAs) that can disrupt grid protect…

The paper evaluates quantum machine learning for detecting anomalies in UAVs using a rigorous, leakage-free methodology, showing that a hybrid XGBoost + Data Reuploading classifier performs well, part…

This paper systematically analyzes 48 studies on perception attacks against autonomous vehicles, revealing that the increasing reliance on multi-sensor fusion creates new, complex vulnerabilities that…

This survey reviews hardware-rooted trust mechanisms, such as PUFs and TPMs, demonstrating that hardware-based solutions are superior to software-only methods for ensuring secure authentication and AI…

The paper introduces a Spatiotemporal-Aware Fault Injection (STAFI) framework to efficiently locate and time critical bit-flip vulnerabilities in DNNs used for ADAS, significantly improving fault dete…

The paper systematically characterizes the fault response of the Intel NCS2 accelerator to electromagnetic fault injection, revealing a major degradation mode that is undetectable by standard inferenc…

The paper analyzes LLM vulnerability detection using mechanistic interpretability, finding that models primarily rely on safety detectors rather than direct vulnerability signature recognition.

TriSweep proposes a novel four-drone swarm framework for autonomous, standoff electromagnetic side-channel analysis, achieving high key rank recovery even with significant signal degradation and jitte…