This paper presents a novel approach for constructing information flow paths from RTL trace data for automated property generation and validation in hardware design.

This paper introduces a high-fidelity, integrated hardware-software simulator for LPDDR5X-PIM, enabling precise evaluation of system performance and energy efficiency.

This paper introduces BigPower, a hierarchical source-level surrogate model for fine-grained module-level power estimation during CPU design using large language models and architectural hierarchy.

The paper proposes a UEFI system utilizing SPDM to authenticate connected PCIe and USB devices, successfully demonstrating that this enhanced security mechanism introduces an acceptable processing ove…

This paper proposes LMS-AR, a memory bandwidth regulation mechanism for multi-core systems using a Linux kernel module with adaptive filtering for prediction and regulation.

This paper systematizes two decades of hardware reverse engineering research by analyzing 187 publications, identifying key technical methods and recommending improvements for reproducibility, standar…

This paper demonstrates a software-only attack chain on EPYC Milan that extracts the hardware root seed, thereby undermining the security guarantees of AMD's SEV-SNP by allowing the forging of valid a…

The paper implements and evaluates several hardware priority queue architectures on modern FPGA platforms and provides a quantitative analysis.

This paper presents multiword arithmetic, a type of multiprecision arithmetic that uses parallel computing to improve efficiency and accuracy, and provides code implementation in PHCpack.

This paper argues that idle cores on contemporary multicore processors can return compute capacity and proposes a budget-centric view of service core systems.

This paper presents an open-source tool for generating efficient hardware parsers from high-level specifications using a decoupled parsing intermediate representation and custom symbolic tokens.

This paper introduces phase-to-primitive decomposition to enable Monte Carlo tree search (MCTS) on in-memory computing (IMC) systems, achieving significant energy efficiency and performance improvemen…

The paper proposes using hardware fingerprints instead of vulnerable cryptographic keys to enhance the security and robustness of GPU location verification for governing advanced AI development.

The paper systematically characterizes the fault response of the Intel NCS2 accelerator to electromagnetic fault injection, revealing a major degradation mode that is undetectable by standard inferenc…

Valinor is a hardware-OS cooperative memory allocation substrate that introduces a programmable hardware allocation engine for improving performance and reducing energy consumption in virtual-to-physi…

The paper introduces BLADEI, a hardware-accelerated framework that screens FPGA configuration bitstreams for anomalies in real-time, overcoming the latency bottleneck of traditional software-based det…

The paper introduces PVAC, a novel victim-based row counting mechanism that accurately tracks RowHammer attacks by incrementing counters on the victim row, thereby improving hammering tolerance and pe…

The paper characterizes 'dead-entry' TLB misses in GPUs, which occur when recently evicted translations are immediately re-walked, and proposes DEPOT, a Bloom filter mechanism that significantly reduc…