Chandan Karfa
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126
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Crypto×1
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2026
Controller Datapath Aware Verification of Masked Hardware Generated via High Level Synthesis
The paper proposes MaskedHLSVerif, a novel formal verification toolflow that accurately verifies the Power Side Channel Attack (PSCA) security of masked hardware generated by High Level Synthesis (HLS), specifically addressing false positives caused by resource-shared datapath architectures.
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