Jude Haris
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This paper optimizes data transfer between host and accelerator in machine learning workloads by eliminating redundant staging operations.
SECDA-DSE is a framework that uses Large Language Models to guide the design space exploration of FPGA-based accelerators for AI workloads.
This paper presents FlexViT, a reconfigurable FPGA accelerator for efficient Vision Transformer (ViT) inference on edge devices, achieving up to 2.74x speedup on accelerator-executed layers.
Papers
FlexViT: A Flexible FPGA-based Accelerator for Edge Vision Transformers
Hubert Dymarkowski, Xingjian Fu, Rappy Saha, Jude Haris +1 more
This paper presents FlexViT, a reconfigurable FPGA accelerator for efficient Vision Transformer (ViT) inference on edge devices, achieving up to 2.74x speedup on accelerator-executed layers.