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Home/Authors/Lorenzo Leone

Lorenzo Leone

1 indexed paper

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Publications per year

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26

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Architecture×1

Frequent co-authors

Philip Wiese1×
Gamze İslamoğlu1×
Michael Rogenmoser1×
Davide Rossi1×
Francesco Conti1×
Luca Benini1×

Research Timeline

2026
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees

The paper introduces Chimera, a highly efficient and scalable MCU designed for ultra-low-power edge AI inference, achieving 3.1 TOPS/W by integrating a dedicated transformer accelerator and a QoS-guaranteed shared L2 memory subsystem.

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Papers

cs.ARRecentJun 1, 2026

CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees

Lorenzo Leone, Philip Wiese, Gamze İslamoğlu, Michael Rogenmoser +3 more

The paper introduces Chimera, a highly efficient and scalable MCU designed for ultra-low-power edge AI inference, achieving 3.1 TOPS/W by integrating a dedicated transformer accelerator and a QoS-guar…

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