Wiebren Wijnstra
1 indexed paper
Recent (6 mo)
1With code
0Influential cites
0Benchmarked
0Publications per year
126
Top categories
Architecture×1Systems and Control×1
Frequent co-authors
Research Timeline
2026
Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
This paper presents two loop cache architectures for RISC-V processors to reduce instruction fetches and energy consumption during AI inference.
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