Yijun Shen
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2026
VHDLSuite: Unified Pipeline for LLM VHDL Generation with Data Synthesis and Evaluation
The paper introduces VHDLSuite, an infrastructure for evaluating Large Language Models in VHDL, including a data pipeline, benchmark, and evaluation framework.
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cs.ARcs.AIcs.LGEmpiricalRecentJun 11, 2026
VHDLSuite: Unified Pipeline for LLM VHDL Generation with Data Synthesis and Evaluation
Yijun Shen, Minghao Shao, Yichen Zhao, Zhuoyan Yu +3 more
The paper introduces VHDLSuite, an infrastructure for evaluating Large Language Models in VHDL, including a data pipeline, benchmark, and evaluation framework.
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