This paper compares three neuromorphic core designs for handling weight sparsity in event-driven neural networks and quantifies the performance and energy costs.

The paper presents ExaGEMM, a framework for designing and exploring CPU-native low-bit GEMM via register-resident LUT execution.

A new HLS tool is presented that enables fine-grained pipeline control in a sequential programming model for competitive PPA.

The first formal verification of an out-of-order multiprocessor against an in-order, weak-memory ISA using a core specification and mechanized proofs in Rocq.

This paper presents two loop cache architectures for RISC-V processors to reduce instruction fetches and energy consumption during AI inference.

This paper introduces BigPower, a hierarchical source-level surrogate model for fine-grained module-level power estimation during CPU design using large language models and architectural hierarchy.

Hawkeye is a system that allows perfect, precision-preserving reproduction of GPU-level matrix multiplication operations on a CPU, enabling efficient and trustworthy third-party auditing of machine le…

This paper presents a method for compressing matrices using a RePair straight-line program (SLP), allowing matrix-vector products with time and space proportional to the compressed size, and demonstra…

This paper presents an open-source tool for generating efficient hardware parsers from high-level specifications using a decoupled parsing intermediate representation and custom symbolic tokens.

The paper introduces BOUNDARY FLOW, an LLVM-based framework that enhances kernel fuzzing and analysis by extracting per-task, state-aware data-flow information (arguments and return values) at functio…

HighTide is an evolving, AI-assisted, open-source benchmark suite for VLSI design, providing a comprehensive and scalable platform for hardware development.

The paper introduces Kops, an extension interface for eBPF that allows userspace compilers and kernel modules to introduce new operations without modifying the kernel core, improving performance and r…

The paper proposes n-VM, a novel Layer-1 architecture that unifies multiple heterogeneous virtual machines (VMs) onto a shared consensus and state layer, solving cross-chain fragmentation issues.

This paper introduces a high-fidelity, integrated hardware-software simulator for LPDDR5X-PIM, enabling precise evaluation of system performance and energy efficiency.

The paper presents a solution to enable multiple double arithmetic on NVIDIA A100 tensor cores, which are unsuited for branching operations caused by renormalization.

The paper introduces ProofLoop, a novel ReAct agent that uses a solver-in-the-loop approach to automatically generate and formally verify SystemVerilog Assertions (SVA) from natural language specifica…

This paper presents CopilotVerifier, a tool that generates proofs of correctness for the compiled output of the Copilot runtime verification framework.

The paper presents a field study on deploying large inference workloads on a non-GPU AI accelerator and identifies eight categories of limitations.