20 results for “Block RAMs”
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Jumin Kim, Seungmin Baek, Hwayong Nam, Minbok Wi +2 more
The paper introduces PVAC, a novel victim-based row counting mechanism that accurately tracks RowHammer attacks by incrementing counters on the victim row, thereby improving hammering tolerance and pe…
The paper proposes PrISM, an intersection-based probabilistic mitigation technique that significantly improves the scalability of RowHammer defense at low thresholds by correlating sampled row history…
This paper presents SCP, a cache partitioning design that combines strict eviction isolation with write-shared coherence to mitigate eviction-based cache side channels.
The paper characterizes 'dead-entry' TLB misses in GPUs, which occur when recently evicted translations are immediately re-walked, and proposes DEPOT, a Bloom filter mechanism that significantly reduc…
This paper introduces DiStash, a disaggregated transactional key-value store that enables an application to use a single transaction to manage key-value pairs across different pools of stashes, preven…
Haocong Luo, F. Nisa Bostancı, Ataberk Olgun, Maria Makeenkova +3 more
Ramulator 2.1 is an updated DRAM simulator with improved support for modern features, better usability, and comprehensive testing.
A simple online algorithm is presented for the stacking problem to avoid shifts with a sufficient condition involving stacking area dimension, load/unload points, and maximum items.
The paper analyzes the bit-flip vulnerability of shared KV-cache blocks in LLM serving systems, demonstrating that these blocks are susceptible to silent, persistent, and selective data corruption.
The paper proposes GroundedCache, an evidence-validated cache router that significantly improves the safety of reusing cached semantic answers in RAG systems by requiring multiple gates to validate th…
The paper proposes Rowhammer Vulnerability Counter (RVC), a novel framework that improves RowHammer mitigation by tracking a row's actual vulnerability to bit flips rather than relying on simple activ…
This paper presents a cryptanalytic attack demonstrating that a specific code-based Private Information Retrieval (PIR) scheme can be broken, allowing the server to efficiently determine the requested…
This paper investigates the persistence of a timing side channel through the shared page cache in modern cloud platforms with various isolation mechanisms.
Jae Hyung Ju, Euijun Chung, Hritvik Taneja, Anish Saxena +3 more
This paper proposes TileLens, a system to mitigate read amplification in Large-Granularity Memory Systems (LGMS) for Large Language Model (LLM) inference by adopting a tile-major layout.
The paper systematically evaluates various defense mechanisms against persistent memory attacks on LLM agents, finding that only tool-gating at the memory layer (Memory Sandbox) effectively mitigates…
The paper provides distinguishers for McEliece type cryptosystems with larger row and column weights, and presents a framework to turn distinguishers into key-recovery attacks. It successfully attacks…
The paper proposes a method to improve the performance of fine-grained offloads on servers by overlapping the offload with other requests using server-side routing.
This paper proposes LMS-AR, a memory bandwidth regulation mechanism for multi-core systems using a Linux kernel module with adaptive filtering for prediction and regulation.
Peter Heger, Lech Nieroda, Roland Pabel, Christoph Stollwerk +6 more
RAMSES is a new HPC system that integrates hardware-based memory encryption and state-of-the-art file encryption to deliver high performance and robust security.