This paper investigates the energy efficiency of Large Language Model (LLM) serving using emerging memory technologies, specifically monolithic 3D (M3D) integration, and presents simulation results sh…

PIMID is an execution- and trace-driven full-system simulator for Processing-in-Memory systems, supporting multiple memory technologies, execution models, and placement of processing elements.

The paper introduces PATH, an in-situ indexing architecture for Processing-in-Memory systems that achieves higher throughput, lower tail latency, and fewer memory accesses than state-of-the-art scheme…

This paper introduces a new protection code design for Content Addressable Memory (CAM) to ensure reliability.

This paper introduces phase-to-primitive decomposition to enable Monte Carlo tree search (MCTS) on in-memory computing (IMC) systems, achieving significant energy efficiency and performance improvemen…

This paper proposes a method for selecting optimal error-correction codes (ECCs) for gain-cell embedded dynamic random-access memory (GCRAM) to minimize power consumption under a yield constraint.

The paper introduces memorywire, a vendor-neutral JSON-Schema 2020-12 wire format and reference implementation to standardize and govern agent memory operations across diverse, proprietary agent-memor…

The paper proposes a highly reconfigurable 256x128 in-memory computing array that significantly improves efficiency and performance for analog computing by introducing novel components for ADC, weight…

The paper introduces memorywire, a vendor-neutral JSON-Schema wire format and reference implementation designed to standardize and govern memory operations across disparate agent-memory frameworks.

The paper proposes SAGE, a novelty-aware gate that efficiently controls memory updates in agentic LLMs by classifying new facts as clearly novel, clearly redundant, or uncertain, thereby significantly…

This paper proposes effective constrained coding solutions to the sneak-path problem in resistive random access memories (ReRAMs) using GF$(4)$ and GF$(8)$ codes.

This paper demonstrates that using circuit-level compensation techniques and batch normalization recalibration can mitigate the impact of retention loss on inference accuracy degradation in a single-p…

The authors of Ramulator 2.0 simulator challenge the claims made in a research paper about its performance and propose best practices to avoid simulator usage errors.

This paper systematically evaluates simple baseline approaches for using external memory (like SSDs) to solve difficult search problems, specifically focusing on the performance of immediate duplicate…

This paper tests Memoir, a neural network model with per-sample fast memory, shared slow parameters, variable-depth latent recurrence, and a future-latent energy objective, and compares it to a read-o…

This paper analyzes the impact of long-term and short-term transistor aging on Deep Neural Network (DNN) inference accuracy and proposes an aging-aware retraining methodology to maintain performance e…

The paper proposes an energy-efficient method for implementing lightweight stream ciphers (Trivium and Grain-128a) within a memristive Computation In-Memory-Array (CIM-A) architecture for secure in-me…

The paper introduces a quantitative, cell-level circuit framework to model DRAM vulnerability by linking physical charge leakage and disturbance pathways to system-level security properties like volat…