The paper implements and evaluates several hardware priority queue architectures on modern FPGA platforms and provides a quantitative analysis.

This paper argues that idle cores on contemporary multicore processors can return compute capacity and proposes a budget-centric view of service core systems.

This paper presents a sustainable, low-cost Desktop Virtualization Infrastructure using discarded electronic equipment for digital education.

This paper proposes a method to explore the design space of quantum-classical applications using a formalization of an architectural style, enabling dynamic selection of the most suitable configuratio…

This paper proposes LMS-AR, a memory bandwidth regulation mechanism for multi-core systems using a Linux kernel module with adaptive filtering for prediction and regulation.

The paper proposes a highly reconfigurable 256x128 in-memory computing array that significantly improves efficiency and performance for analog computing by introducing novel components for ADC, weight…

The elasticAI.explorer is an extensible, unified Python framework that simplifies hardware-aware Neural Architecture Search (NAS) by decoupling search space definition from model implementation and de…

The paper presents ExaGEMM, a framework for designing and exploring CPU-native low-bit GEMM via register-resident LUT execution.

This paper proposes a lightweight architectural enhancement for FPGA designs to improve data movement between block RAMs and digital signal processing units for deep learning workloads, incurring negl…

This paper presents an open-source tool for generating efficient hardware parsers from high-level specifications using a decoupled parsing intermediate representation and custom symbolic tokens.

The paper demonstrates that for FFT-based radar imaging on Apple Silicon, the limiting factor for half-precision (FP16) is dynamic range, not mantissa precision, and proposes a block-floating-point (B…

The paper proposes a method to improve the performance of fine-grained offloads on servers by overlapping the offload with other requests using server-side routing.

This paper introduces a high-fidelity, integrated hardware-software simulator for LPDDR5X-PIM, enabling precise evaluation of system performance and energy efficiency.

This paper proposes a new approach for real-time, dynamic and sound quantization and hardware to support it for resource-efficient neural networks and high-precision mathematics on edge devices, ensur…

O-POPE is a novel outer-product engine that accelerates floating-point GEMM by repurposing FPU pipeline registers as buffers, achieving high utilization and improved energy efficiency.

This paper presents multiword arithmetic, a type of multiprecision arithmetic that uses parallel computing to improve efficiency and accuracy, and provides code implementation in PHCpack.

Valinor is a hardware-OS cooperative memory allocation substrate that introduces a programmable hardware allocation engine for improving performance and reducing energy consumption in virtual-to-physi…