Computer Architecture
CPU/GPU design, memory systems, and hardware accelerators
20 papers indexed
A Combined Streaming FPGA Architecture for Client-Side CKKS Encoding and Encryption
A streaming FPGA architecture for CKKS encoding and encryption is presented, achieving high performance and efficiency.
FlexViT: A Flexible FPGA-based Accelerator for Edge Vision Transformers
Hubert Dymarkowski, Xingjian Fu, Rappy Saha, Jude Haris +1 more
This paper presents FlexViT, a reconfigurable FPGA accelerator for efficient Vision Transformer (ViT) inference on edge devices, achieving up to 2.74x speedup on accelerator-executed layers.
NeuronFabric: A Software Reference Architecture for On-Chip Transformer Training with Local Adam
This paper presents NeuronFabric, a software reference architecture for future FPGA and ASIC implementations of transformer training with local Adam updates.
OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
OpenEye is a scalable, sparsity-aware FPGA-based hardware accelerator designed to efficiently execute common deep neural network operations, demonstrating favorable performance-resource trade-offs acr…
Sparse by Command: Task-Conditional Compute Skipping for Multi-Task Inference Accelerators
Afzal Ahmad, Gaoyu Mao, Shoubo Hu, Hui-Ling Zhen +3 more
A co-designed hardware-software approach for task-conditional sparsity in multi-task inference models, reducing FLOPs, latency, and energy.
Towards Autonomous Accelerator Design: FPGA Accelerator Generation with SECDA
SECDA-DSE is a framework that uses Large Language Models to guide the design space exploration of FPGA-based accelerators for AI workloads.
Triple-Hoisted Baby-Step Giant-Step Linear Transformation over CKKS Homomorphic Encryption and Hardware Accelerator
The paper proposes a novel triple-hoisted baby-step giant-step algorithm and a memory-optimized FPGA accelerator to significantly reduce the ciphertext rotations and off-chip memory access latency whe…
A Heterogeneous Neural Network Accelerator for End-to-End Multitask RF Signal Recognition
This paper proposes a heterogeneous neural network accelerator for multi-task RF signal recognition, achieving high accuracy and low latency for automatic modulation recognition, hardware-Trojan cover…
ExSpike: A General Full-Event Neuromorphic Architecture for Exploiting Irregular Sparsity with Event Compression
This paper proposes a new full-event neuromorphic architecture called ExSpike that exploits irregular sparsity in spiking neural networks for energy-efficient computing.
ReSCom: A Reconfigurable Spiking Neural Network Accelerator Using Stochastic Computing
This paper presents ReSCom, a reconfigurable SNN accelerator that leverages stochastic computing to reduce hardware complexity while maintaining stable inference.
Randomized Caches in Hardware: Challenges and Trade-offs
Xinrui Wang, Pascal Kosak, Christof Paar, Daniel Genkin +2 more
This paper implements and evaluates four randomized cache designs to protect against side-channel attacks.
Operating System Support for Accelerators as First-Class Compute Elements in Heterogeneous Systems
This paper presents a framework called MEERKAT to mitigate inefficiencies in heterogeneous systems-on-chip by migrating Linux OS support from software to hardware.
RAMSES: Secure high-performance computing for sensitive data
Peter Heger, Lech Nieroda, Roland Pabel, Christoph Stollwerk +6 more
RAMSES is a new HPC system that integrates hardware-based memory encryption and state-of-the-art file encryption to deliver high performance and robust security.
On-Device Generative AI for GDPR-Compliant Visual Monitoring: Natural Language Alerts from Local Object Detection
The paper proposes a privacy-preserving visual monitoring system that performs object detection and generates natural language alerts entirely on an edge device, ensuring GDPR compliance by never tran…
Design and Evaluation of Energy-Efficient Whisper Dot-Product Kernel Offloading on a CGLA Architecture
This paper implements and evaluates Whisper dot-product kernel offloading on a programmable Coarse-Grained Linear Arrays (CGLAs) architecture to reduce power consumption.
Feasibility of Time-Domain DNN-Based Speech Enhancement on Embedded FPGA for Hearing Aid
This paper characterizes the gap between current DNN-based speech enhancement systems and hearing aid constraints, and proposes a lightweight architecture to meet these constraints.
Rotary GPU: Exploring Local Execution Paths for Large Mixture-of-Experts Models Under Limited GPU Memory
The paper introduces Rotary GPU, an exploratory execution approach demonstrating that large Mixture-of-Experts models can be run locally on consumer GPUs with limited VRAM, achieving usable decode thr…
Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
A new compression technique is introduced to reduce memory footprint on FPGAs by saving weights in deltas with lower bitwidth.
Defeat the Heap: Zero-Copy Data Movement in AXI4MLIR
Elam Cohavi, Nicolas Bohm Agostini, Jude Haris, Antonino Tumeo +2 more
This paper optimizes data transfer between host and accelerator in machine learning workloads by eliminating redundant staging operations.
SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network Accelerators through Co-Optimized Mapping and Scheduling
This paper introduces SupraSNN, a superscalar-inspired architecture for efficient execution of Spiking Neural Networks (SNNs) on physical hardware.