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Home/Authors/Onur Mutlu

Onur Mutlu

13 indexed papers

Recent (6 mo)
11
With code
0
Influential cites
0
Benchmarked
0

Publications per year

13
26

Top categories

Architecture×12Distributed×6Crypto×4Other Quantitative Biology×1Performance×1

Frequent co-authors

Ataberk Olgun6×
Haocong Luo5×
Mohammad Sadrosadati4×
Abdullah Giray Yağlıkçı3×
Yilong Zhao2×
Fangxin Liu2×

Research Timeline

2026
HE-PIM: Demystifying Homomorphic Operations on a Real-world Processing-in-Memory System

The paper characterizes Homomorphic Encryption (HE) operations on a real-world Processing-In-Memory (PIM) system, demonstrating that while PIM is a viable alternative to CPUs/GPUs, performance is limited by the lack of native modular multiplication and insufficient per-bank memory capacity.

Taking Cryptography Out of the Data Path via Near-Memory Processing in DRAM

This paper investigates the potential of real-world Processing-in-Memory (PIM) architectures, specifically using UPMEM, to accelerate cryptographic algorithms, demonstrating that distributing computation across multiple memory ranks significantly improves performance.

Ramulator 2.1: A Composable Memory System Simulator for Modern DRAM Systems

Ramulator 2.1 is an updated DRAM simulator with improved support for modern features, better usability, and comprehensive testing.

Extended Abstract: Re-Evaluating the Real-System Modeling Accuracy of Ramulator 2.0

The authors of Ramulator 2.0 simulator challenge the claims made in a research paper about its performance and propose best practices to avoid simulator usage errors.

PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems

This paper investigates and mitigates the interference phenomenon PuDGhost in Processing-using-DRAM (PuD) systems.

DejaVu: Why You Should Write to Your DRAM Rows Twice, Carefully

The paper demonstrates the DejaVu phenomenon in DRAM cells and its effects on read disturbance vulnerability.

Architecture for Health Initiative (Arch4Health): Computational Challenges in Health-Related Applications and the Role of Computer Architecture in Addressing Them

The Arch4Health initiative aims to optimize computing systems for high-performance, energy-efficient, low-cost, private, and secure analysis of biological data.

Clutch: High Performance Vector-Scalar Comparison using DRAM via Chunked Temporal Coding

This paper proposes Clutch, a method to accelerate vector-scalar comparisons in Processing-using-DRAM systems.

COSM: A Cooperative Scheduling Framework for Concurrent PIM and CPU Execution on Mobile Devices

The paper introduces COSM, a cooperative scheduling framework to facilitate concurrent operation of Processing-in-Memory (PIM) and CPU tasks on mobile platforms, improving PIM throughput by up to 2.8x with less than 2.0% CPU performance loss.

Valinor: Architectural Support for Fast, Energy-Efficient and Programmable Physical Memory Allocation

Valinor is a hardware-OS cooperative memory allocation substrate that introduces a programmable hardware allocation engine for improving performance and reducing energy consumption in virtual-to-physical mappings.

Exploring High-Bandwidth Flash for Modern LLM Inference: Opportunities and Challenges

This paper investigates the benefits and challenges of using high-bandwidth flash for large language model inference, showing potential for increased batch size, throughput, and flexibility.

HULK: An Efficient Algorithm for Enabling Fast Bulk Bitwise Operations on Homomorphically Encrypted Data

This paper proposes HULK, an efficient homomorphic encryption algorithm that enables fast bulk bitwise operations on encrypted data.

GUMPIM: Unitary and Malleable Memory for Processing-in-Memory with Guaranteed PIM Pages

This paper proposes GUMPIM, a PIM system that enables interleaved CPU and PIM pages to coexist in a single memory space.

Highlighted terms show continued research focus across papers

Papers

cs.AREmpiricalRecentOct 16, 2026

GUMPIM: Unitary and Malleable Memory for Processing-in-Memory with Guaranteed PIM Pages

Yilong Zhao, Fangxin Liu, Yiwei Hu, Zongwu Wang +12 more

This paper proposes GUMPIM, a PIM system that enables interleaved CPU and PIM pages to coexist in a single memory space.

View →
cs.CRcs.ARcs.DCEmpirical
Recent
Oct 13, 2026

HULK: An Efficient Algorithm for Enabling Fast Bulk Bitwise Operations on Homomorphically Encrypted Data

Mayank Kabra, Phillip Widdowson, Harshita Gupta, Rakesh Nadig +8 more

This paper proposes HULK, an efficient homomorphic encryption algorithm that enables fast bulk bitwise operations on encrypted data.

View →
cs.AREmpiricalRecentAug 14, 2026

Exploring High-Bandwidth Flash for Modern LLM Inference: Opportunities and Challenges

Dowon Son, Yonggon Park, Hyunuk Cho, Hyungkyu Ham +4 more

This paper investigates the benefits and challenges of using high-bandwidth flash for large language model inference, showing potential for increased batch size, throughput, and flexibility.

View →
cs.AREmpiricalRecentJul 16, 2026

Valinor: Architectural Support for Fast, Energy-Efficient and Programmable Physical Memory Allocation

Konstantinos Kanellopoulos, Spiros Galanopoulos, Konstantinos Sgouras, Vlad-Petru Nitu +6 more

Valinor is a hardware-OS cooperative memory allocation substrate that introduces a programmable hardware allocation engine for improving performance and reducing energy consumption in virtual-to-physi…

View →
cs.ARcs.DCEmpiricalRecentJun 29, 2026

COSM: A Cooperative Scheduling Framework for Concurrent PIM and CPU Execution on Mobile Devices

Yilong Zhao, Fangxin Liu, Onur Mutlu, Mingyu Gao +3 more

The paper introduces COSM, a cooperative scheduling framework to facilitate concurrent operation of Processing-in-Memory (PIM) and CPU tasks on mobile platforms, improving PIM throughput by up to 2.8x…

View →
cs.ARcs.DCEmpiricalRecentJun 22, 2026

Clutch: High Performance Vector-Scalar Comparison using DRAM via Chunked Temporal Coding

Daichi Tokuda, Tatsuya Kubo, Ismail Emir Yuksel, Ataberk Olgun +7 more

This paper proposes Clutch, a method to accelerate vector-scalar comparisons in Processing-using-DRAM systems.

View →
cs.ARcs.CREmpiricalRecentJun 21, 2026

DejaVu: Why You Should Write to Your DRAM Rows Twice, Carefully

Haocong Luo, İsmail Emir Yüksel, Ataberk Olgun, Nisa Bostanci +3 more

The paper demonstrates the DejaVu phenomenon in DRAM cells and its effects on read disturbance vulnerability.

View →
cs.ARcs.DCq-bio.OTPositionRecentJun 21, 2026

Architecture for Health Initiative (Arch4Health): Computational Challenges in Health-Related Applications and the Role of Computer Architecture in Addressing Them

Nika Mansouri Ghiasi, Konstantina Koliogeorgi, Onur Mutlu

The Arch4Health initiative aims to optimize computing systems for high-performance, energy-efficient, low-cost, private, and secure analysis of biological data.

View →
cs.ARcs.DCEmpiricalRecentJun 17, 2026

PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems

Daichi Tokuda, İsmail Emir Yüksel, Tatsuya Kubo, Ataberk Olgun +6 more

This paper investigates and mitigates the interference phenomenon PuDGhost in Processing-using-DRAM (PuD) systems.

View →
cs.ARcs.PFEmpiricalRecentJun 12, 2026

Extended Abstract: Re-Evaluating the Real-System Modeling Accuracy of Ramulator 2.0

F. Nisa Bostanci, Haocong Luo, Ataberk Olgun, Maria Makeenkova +3 more

The authors of Ramulator 2.0 simulator challenge the claims made in a research paper about its performance and propose best practices to avoid simulator usage errors.

View →
cs.AREmpiricalRecentJun 11, 2026

Ramulator 2.1: A Composable Memory System Simulator for Modern DRAM Systems

Haocong Luo, F. Nisa Bostancı, Ataberk Olgun, Maria Makeenkova +3 more

Ramulator 2.1 is an updated DRAM simulator with improved support for modern features, better usability, and comprehensive testing.

View →
cs.CRcs.ARcs.DCMay 19, 2026

Taking Cryptography Out of the Data Path via Near-Memory Processing in DRAM

Nicola Barcarolo, Brahmaiah Gandham, Mohammad Sadrosadati, Roberto Passerone +2 more

This paper investigates the potential of real-world Processing-in-Memory (PIM) architectures, specifically using UPMEM, to accelerate cryptographic algorithms, demonstrating that distributing computat…

View →
cs.CRMay 13, 2026

HE-PIM: Demystifying Homomorphic Operations on a Real-world Processing-in-Memory System

Harshita Gupta, Mayank Kabra, Jaewoo Park, Priyam Mehta +8 more

The paper characterizes Homomorphic Encryption (HE) operations on a real-world Processing-In-Memory (PIM) system, demonstrating that while PIM is a viable alternative to CPUs/GPUs, performance is limi…

View →