Weihua Xiao
2 indexed papers
Recent (6 mo)
2With code
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226
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AI×2ML×1Neural Computing×1Architecture×1Crypto×1
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2026
VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog
VeriCWEty proposes an embedding-based framework to detect and classify common software vulnerabilities (CWEs) in Verilog RTL code at both module and line levels, achieving high detection accuracy.
CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models
This paper presents CoEvoP&R, a framework that uses a large language model to automatically evolve analytical placement objectives, reducing post-route routed wirelength, congestion, and improving timing quality.
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Papers
cs.LGcs.AIcs.NEEmpiricalRecentJul 19, 2026
CoEvoP&R: Co-Evolving Placement Objectives with Routing Feedback via Large Language Models
This paper presents CoEvoP&R, a framework that uses a large language model to automatically evolve analytical placement objectives, reducing post-route routed wirelength, congestion, and improving tim…
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cs.ARcs.AIcs.CRRecent