Weihua Xiao
1 indexed paper
Recent (6 mo)
1With code
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126
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Architecture×1AI×1Crypto×1
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2026
VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog
VeriCWEty proposes an embedding-based framework to detect and classify common software vulnerabilities (CWEs) in Verilog RTL code at both module and line levels, achieving high detection accuracy.
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