Zeng Wang
2 indexed papers
Recent (6 mo)
2With code
0Influential cites
0Benchmarked
0Publications per year
226
Top categories
Crypto×2Architecture×1AI×1
Frequent co-authors
Research Timeline
2026
VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog
VeriCWEty proposes an embedding-based framework to detect and classify common software vulnerabilities (CWEs) in Verilog RTL code at both module and line levels, achieving high detection accuracy.
HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking
The paper introduces HarmChip, a novel benchmark to evaluate LLM vulnerability to domain-specific hardware security threats, revealing that current safety guardrails fail against semantically disguised attacks.
Highlighted terms show continued research focus across papers
Papers
cs.CRRecentApr 18, 2026
HarmChip: Evaluating Hardware Security Centric LLM Safety via Jailbreak Benchmarking
Zeng Wang, Minghao Shao, Weimin Fu, Prithwish Basu Roy +5 more
The paper introduces HarmChip, a novel benchmark to evaluate LLM vulnerability to domain-specific hardware security threats, revealing that current safety guardrails fail against semantically disguise…
View →
cs.ARcs.AIcs.CRRecentApr 15, 2026