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~ similar to 2606.03796· 17 results

cs.NEcs.LGRecentJun 2, 2026

Quadratic integrate-and-fire neurons exhibit less fragmented loss landscapes and outperform leaky integrate-and-fire neurons in spike-based gradient descent

Carlo Wenig, Raoul-Martin Memmesheimer, Christian Klos

The paper demonstrates that quadratic integrate-and-fire (QIF) neurons are superior to leaky integrate-and-fire (LIF) neurons for gradient descent training in spiking neural networks because their con…

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cs.CRcs.AIcs.LGRecentMay 21, 2026

Characterizing the Fault Response of the Intel Neural Compute Stick 2 Under Single-Pulse Electromagnetic Fault Injection

Štefan Kučerák, Jakub Breier, Xiaolu Hou

The paper systematically characterizes the fault response of the Intel NCS2 accelerator to electromagnetic fault injection, revealing a major degradation mode that is undetectable by standard inferenc…

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cs.CRcs.LGRecentMar 25, 2026

Efficient Encrypted Computation in Convolutional Spiking Neural Networks with TFHE

Longfei Guo, Pengbo Li, Ting Gao, Yonghai Zhong +2 more

The paper introduces FHE-DiCSNN, a novel framework that uses the TFHE scheme to enable secure and efficient computation on Spiking Neural Networks (SNNs), achieving high accuracy and fast inference ti…

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cs.ARcs.ETRecentMay 27, 2026

Nonvolatile Charge-Domain Attention with HZO Ferroelectric Capacitors: A Simulation-Based Device-to-System Evaluation

Faris Abouagour

The paper proposes a Ferroelectric Charge-Domain Compute Cell (FCDC) using HZO memcapacitors to perform attention computation, achieving significant energy efficiency gains, especially for long-reside…

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cs.ARcs.AIcs.NERecentJun 4, 2026

ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training

Haihang Xia, Xinyu Zhao, Xuecheng Wang, John Goodenough +4 more

This paper proposes and validates a novel hardware architecture, ITP-STDP, to significantly reduce the energy consumption and hardware overhead associated with training Spiking Neural Networks (SNNs).

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cs.CRcs.AIRecentMay 21, 2026

A Constant-Time Implementation Methodology for Activation Functions on Microcontrollers

Andrii Tyvodar, Andreas Rechberger, Dirmanto Jap, Shivam Bhasin +3 more

The paper proposes a constant-time implementation methodology for activation functions on microcontrollers to prevent timing side-channel attacks during embedded neural-network inference.

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cs.CRcs.SERecentMar 19, 2026

CNT: Safety-oriented Function Reuse across LLMs via Cross-Model Neuron Transfer

Yue Zhao, Yujia Gong, Ruigang Liang, Shenchen Zhu +3 more

The paper introduces Cross-Model Neuron Transfer (CNT), a post-hoc method that efficiently transfers safety-oriented functionalities between different large language models by transferring minimal sub…

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cs.CRRecentMay 13, 2026

Phantom Force: Injecting Adversarial Tactile Perceptions into Embodied Intelligence via EMI

Zirui Kong, Youqian Zhang, Sze Yiu Chau

This paper investigates a novel vulnerability in tactile sensing by demonstrating that targeted Electromagnetic Interference (EMI) can induce strong, misleading 'phantom forces' in Hall-effect fingert…

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eess.SPcs.AIcs.LGRecentMay 28, 2026

SpikeWFM: Spiking-Aided Wireless Foundation Model for Robust Channel Prediction

Liwen Jing, Yisha Lu, Tingting Yang, Li Sun +4 more

The paper introduces SpikeWFM, a novel hybrid architecture combining spiking neural networks (SNNs) and transformers, which significantly improves the robustness and accuracy of wireless foundation mo…

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cs.CRcs.AIcs.NERecentMay 31, 2026

On the Evaluation of Spiking Neural Network Configurations for Network Intrusion Detection

Raj Patel, David Amebley, Taye Akinrele, Shaswata Mitra +2 more

The paper systematically evaluates 27 Spiking Neural Network (SNN) configurations to determine the optimal combination of neuron model and spike encoding scheme for network intrusion detection, findin…

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cs.CRcs.AIcs.NERecentMay 31, 2026

On the Evaluation of Spiking Neural Network Configurations for Network Intrusion Detection

Raj Patel, David Amebley, Taye Akinrele, Shaswata Mitra +2 more

The paper evaluates 27 different Spiking Neural Network (SNN) configurations to determine the optimal design for network intrusion detection, finding that the LeakyParallel neuron combined with latenc…

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cs.AREmpiricalRecentJun 10, 2026

BenDi: An Energy-Efficient Quasi-Stochastic Systolic Architecture for Edge Bioelectronics

Bochen Ye, Yihan Pan, Shady Agwa, Themis Prodromakis

This paper presents BenDi, an energy-efficient quasi-stochastic systolic architecture for bioelectronic systems on the edge.

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cs.CRcs.AIcs.DCRecentMay 31, 2026

AMP: A Vendor-Neutral Wire Format for Agent Memory Operations

Thamilvendhan Munirathinam

The paper introduces memorywire, a vendor-neutral JSON-Schema wire format and reference implementation designed to standardize and govern memory operations across disparate agent-memory frameworks.

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cs.LGcs.AIRecentMay 31, 2026

PALTO: Physics-Informed Active Learning for Tri-Gate FinFET Design Optimization for Vertical Power Delivery

Ayoub Sadeghi, Leonid Popryho, Inna Partin-Vaisband

The paper introduces a physics-informed active learning framework to optimize GaN tri-gate FinFETs for vertical power delivery, identifying a multi-fin device (D1) that significantly outperforms a sin…

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cs.LOcs.AIRecentMay 28, 2026

Neural Network Verification using Partial Multi-Neuron Relaxation

Ido Shmuel, Guy Katz

The paper introduces partial multi-neuron relaxation, a novel verification technique that selectively computes tight linear bounds for a small subset of neurons to improve the efficiency and tightness…

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cs.ARRecentMay 28, 2026

Constant Depth Threshold Circuits For Exhaustive Epistasis Detection

André Ribeiro, Aleksandar Ilic, Leonel Sousa

The paper proposes constant depth threshold circuits for efficiently detecting epistasis by calculating the relative frequencies of all dataset combinations using specialized hardware architectures.

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cs.CVcs.CRRecentApr 6, 2026

Lightweight True In-Pixel Encryption with FeFET Enabled Pixel Design for Secure Imaging

Md Rahatul Islam Udoy, Diego Ferrer, Wantong Li, Kai Ni +2 more

The paper proposes SecurePix, a compact CMOS-compatible pixel architecture that achieves true in-pixel encryption using FeFETs, demonstrating strong image security and low power overhead.

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