This paper enhances open-source FPGA CAD tools to model and explore inter-die routing architectures for 2.5D and 3D FPGAs, demonstrating that these architectures can significantly improve performance…

The paper introduces BLADEI, a hardware-accelerated framework that screens FPGA configuration bitstreams for anomalies in real-time, overcoming the latency bottleneck of traditional software-based det…

This paper proposes a resource-oriented one-shot quantiser pruning method for high granularity quantisation (HGQ) to reduce search cost and achieve a competitive Pareto frontier in FPGA-based edge neu…

The paper characterizes 'dead-entry' TLB misses in GPUs, which occur when recently evicted translations are immediately re-walked, and proposes DEPOT, a Bloom filter mechanism that significantly reduc…

Tessera introduces a novel hardware architecture that achieves secure, near-line-rate weight streaming for DNNs on UMA edge accelerators by performing cache-line granularity decryption during DRAM fet…

The paper proposes a novel convolutional block and optimization algorithm to implement resource-efficient 1D-CNNs for atrial fibrillation detection on tiny smart sensor systems, achieving high accurac…

This paper presents FlexViT, a reconfigurable FPGA accelerator for efficient Vision Transformer (ViT) inference on edge devices, achieving up to 2.74x speedup on accelerator-executed layers.

This paper presents two loop cache architectures for RISC-V processors to reduce instruction fetches and energy consumption during AI inference.

OpenEye is a scalable, sparsity-aware FPGA-based hardware accelerator designed to efficiently execute common deep neural network operations, demonstrating favorable performance-resource trade-offs acr…

The paper implements and evaluates several hardware priority queue architectures on modern FPGA platforms and provides a quantitative analysis.

The paper proposes a highly reconfigurable 256x128 in-memory computing array that significantly improves efficiency and performance for analog computing by introducing novel components for ADC, weight…

The paper presents CHASE, an application-driven framework that explores physically feasible Cross-layer Heterogeneous System architectures for executing workloads with diverse requirements.

This paper addresses the obstacles of using Crossbar-based In-Memory Processing (IMP) accelerators for deep neural networks (DNNs) by reusing bit-shift units for multiplication, applying pruning metho…