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20 results for “GPU memory hierarchy”

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cs.AREmpiricalRecentJul 22, 2026

DGNA: Dissecting GPU NUMA Architecture through Microbenchmarking and Data Analysis

Changxi Liu, Yun Chen, Trevor E. Carlson

This paper introduces DGNA, a methodology to unveil the Non-Uniform Memory Access (NUMA) architecture of GPU memory hierarchy through microbenchmarking and data analysis.

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cs.DCcs.PFEmpiricalRecentJul 24, 2026

TileSight: A First-Principles Tile-Centric Analytical GPU Performance Model from Cores to Clusters

Zhiwen Mo, Yu Cheng, Lei Wang, Zhengju Tang +11 more

TileSight is a tile-centric performance-modeling tool that predicts single-GPU kernel latency and cache hit rates with low error, outperforming state-of-the-art baselines and transferring well across…

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cs.DCcs.LGEmpiricalRecentJul 19, 2026

Taurus: Accelerating Out-of-Core Graph Neural Network Inference on Billion-Scale Graphs

Pranjal Naman, Yogesh Simmhan

Taurus is a single-machine system for efficient Graph Neural Network (GNN) inference on large-scale graphs that do not fit in RAM, using source-centric broadcasts and a pipelined GPU-CPU-SSD hierarchy…

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cs.DCEmpiricalRecentJul 24, 2026

$g$MAGNUS: Fast SpGEMM on GPUs for Irregular Matrices via Hierarchical Multisplit

Jordi Wolfson-Pou, Ahmed Helal, Fabrizio Petrini

The paper introduces $g$MAGNUS, a new algorithm for sparse matrix-matrix multiplication on GPUs that addresses heavy rows by reordering intermediate products and achieves significant speedups.

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cs.ARcs.PFRecentMay 30, 2026

Regular-Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures

Shafayat Mowla Anik, Yongchan Jung, Jeeho Ryoo, Byeong Kil Lee

The paper characterizes 'dead-entry' TLB misses in GPUs, which occur when recently evicted translations are immediately re-walked, and proposes DEPOT, a Bloom filter mechanism that significantly reduc…

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cs.AREmpiricalRecentJul 4, 2026

TileLens: Efficiently Using Large-Granularity Memory Systems with Transparent Two-Dimensional Memory Layout

Jae Hyung Ju, Euijun Chung, Hritvik Taneja, Anish Saxena +3 more

This paper proposes TileLens, a system to mitigate read amplification in Large-Granularity Memory Systems (LGMS) for Large Language Model (LLM) inference by adopting a tile-major layout.

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cs.GRcs.CVcs.DCEmpiricalRecentJul 17, 2026

Rendering 3D Gaussians on a Graph Processor

Nicholas Fry, Ignacio Alzugaray, Mark Pupilli, Paul H. J. Kelly +1 more

First implementation of a 3D Gaussian renderer on an Intelligence Processing Unit (IPU) with 1,472 independent tiles using only on-chip SRAM.

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cs.DCcs.LGEmpiricalRecentJun 29, 2026

GPU Parallelization Strategies for Forward and Backward Propagation in Shallow Neural Networks: A CUDA-Based Comparative Study

Rania Zitouni, Nadine Bousdjira, Sarah Hasnaoui, Amel Sadoun +1 more

This paper compares and optimizes CUDA strategies for a shallow neural network, achieving a 1.41x speedup on a large dataset.

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cs.DScs.DCcs.MSEmpiricalRecentJul 27, 2026

Right Multiplication on Grammar-Compressed Matrices: A Streaming, Memory-Bounded GPU Engine

Francesco Tosoni, Gabriele Mencagli

This paper presents a method for compressing matrices using a RePair straight-line program (SLP), allowing matrix-vector products with time and space proportional to the compressed size, and demonstra…

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eess.SPcs.DCEmpiricalRecentJul 26, 2026

Parallel Cascaded Recursive Filtering on Multi-Core CPUs and GPUs

Haotian Zhai, Bernd-Peter Paris

This paper reformulates cascaded second-order filtering as a block-tridiagonal linear system and develops parallel solution algorithms, achieving high performance on SIMD cores, multi-core CPUs, and G…

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cs.PFcs.ARcs.DCRecentMay 27, 2026

Rotary GPU: Exploring Local Execution Paths for Large Mixture-of-Experts Models Under Limited GPU Memory

Myeong Jun Jo

The paper introduces Rotary GPU, an exploratory execution approach demonstrating that large Mixture-of-Experts models can be run locally on consumer GPUs with limited VRAM, achieving usable decode thr…

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cs.DCEmpiricalRecentJul 24, 2026

Agentic CPU-GPU Scheduling for Heterogeneous AI Workloads

Tianxi Lu, Sherief Reda

This paper identifies suboptimalities in default GPU-first scheduling for AI tool workloads and proposes an agentic scheduler that adaptively assigns tools to GPU or CPU based on runtime factors.

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cs.ARcs.AIcs.ETEmpiricalRecentJul 24, 2026

Multi-primitive in-memory computing for Monte Carlo tree search

Tergel Molom-Ochir, Benjamin F. Morris, Yintao He, Archit Gajjar +5 more

This paper introduces phase-to-primitive decomposition to enable Monte Carlo tree search (MCTS) on in-memory computing (IMC) systems, achieving significant energy efficiency and performance improvemen…

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cs.PFcs.ARcs.DCRecentMay 28, 2026

From Roofline to Ruggedness: Decomposing and Smoothing the GEMM Performance Landscape

Aditya Chatterjee

The paper introduces performance ruggedness analysis to quantify performance variance in GEMM workloads, proposing a two-stage software stack that significantly smooths the performance landscape and b…

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cs.AREmpiricalRecentJun 16, 2026

CUTh-Solver: GPU-Accelerated Sparse Matrix Solver for High-Resolution Thermal Simulation of 3D ICs

Chenghan Wang, Zhen Zhuang, Shui Jiang, Siyuan Liang +8 more

This paper proposes CUTh-Solver, a GPU-accelerated Preconditioned Conjugate Gradient (PCG)-based sparse solver framework for high-resolution 3D IC thermal simulation, achieving significant speedup ove…

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cs.AREmpiricalRecentJul 16, 2026

Valinor: Architectural Support for Fast, Energy-Efficient and Programmable Physical Memory Allocation

Konstantinos Kanellopoulos, Spiros Galanopoulos, Konstantinos Sgouras, Vlad-Petru Nitu +6 more

Valinor is a hardware-OS cooperative memory allocation substrate that introduces a programmable hardware allocation engine for improving performance and reducing energy consumption in virtual-to-physi…

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cs.ARcs.LGEmpiricalRecentJun 11, 2026

BigPower: Hierarchical Source-Level Module Power Estimation for CPUs with Large Language Models

Honghua Zhu, Chunjie Luo, Jianfeng Zhan

This paper introduces BigPower, a hierarchical source-level surrogate model for fine-grained module-level power estimation during CPU design using large language models and architectural hierarchy.

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cs.DCcs.DSEmpiricalRecentJul 22, 2026

Fully Dynamic Rooted Spanning Tree on GPU

Abhijeet Sahu, Harmit Singh, Soham Nandy, G. Ramakrishna

This paper presents four novel parallel algorithms for maintaining a rooted spanning forest in dynamic graphs, achieving a throughput of 2 million insertions and 1.4 million deletions per second.

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