20 results for “GPU memory hierarchy”
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This paper introduces DGNA, a methodology to unveil the Non-Uniform Memory Access (NUMA) architecture of GPU memory hierarchy through microbenchmarking and data analysis.
Zhiwen Mo, Yu Cheng, Lei Wang, Zhengju Tang +11 more
TileSight is a tile-centric performance-modeling tool that predicts single-GPU kernel latency and cache hit rates with low error, outperforming state-of-the-art baselines and transferring well across…
Taurus is a single-machine system for efficient Graph Neural Network (GNN) inference on large-scale graphs that do not fit in RAM, using source-centric broadcasts and a pipelined GPU-CPU-SSD hierarchy…
The paper introduces $g$MAGNUS, a new algorithm for sparse matrix-matrix multiplication on GPUs that addresses heavy rows by reordering intermediate products and achieves significant speedups.
The paper characterizes 'dead-entry' TLB misses in GPUs, which occur when recently evicted translations are immediately re-walked, and proposes DEPOT, a Bloom filter mechanism that significantly reduc…
Jae Hyung Ju, Euijun Chung, Hritvik Taneja, Anish Saxena +3 more
This paper proposes TileLens, a system to mitigate read amplification in Large-Granularity Memory Systems (LGMS) for Large Language Model (LLM) inference by adopting a tile-major layout.
First implementation of a 3D Gaussian renderer on an Intelligence Processing Unit (IPU) with 1,472 independent tiles using only on-chip SRAM.
Rania Zitouni, Nadine Bousdjira, Sarah Hasnaoui, Amel Sadoun +1 more
This paper compares and optimizes CUDA strategies for a shallow neural network, achieving a 1.41x speedup on a large dataset.
This paper presents a method for compressing matrices using a RePair straight-line program (SLP), allowing matrix-vector products with time and space proportional to the compressed size, and demonstra…
This paper reformulates cascaded second-order filtering as a block-tridiagonal linear system and develops parallel solution algorithms, achieving high performance on SIMD cores, multi-core CPUs, and G…
The paper introduces Rotary GPU, an exploratory execution approach demonstrating that large Mixture-of-Experts models can be run locally on consumer GPUs with limited VRAM, achieving usable decode thr…
This paper identifies suboptimalities in default GPU-first scheduling for AI tool workloads and proposes an agentic scheduler that adaptively assigns tools to GPU or CPU based on runtime factors.
This paper introduces phase-to-primitive decomposition to enable Monte Carlo tree search (MCTS) on in-memory computing (IMC) systems, achieving significant energy efficiency and performance improvemen…
The paper introduces performance ruggedness analysis to quantify performance variance in GEMM workloads, proposing a two-stage software stack that significantly smooths the performance landscape and b…
Chenghan Wang, Zhen Zhuang, Shui Jiang, Siyuan Liang +8 more
This paper proposes CUTh-Solver, a GPU-accelerated Preconditioned Conjugate Gradient (PCG)-based sparse solver framework for high-resolution 3D IC thermal simulation, achieving significant speedup ove…
Valinor is a hardware-OS cooperative memory allocation substrate that introduces a programmable hardware allocation engine for improving performance and reducing energy consumption in virtual-to-physi…
This paper introduces BigPower, a hierarchical source-level surrogate model for fine-grained module-level power estimation during CPU design using large language models and architectural hierarchy.
This paper presents four novel parallel algorithms for maintaining a rooted spanning forest in dynamic graphs, achieving a throughput of 2 million insertions and 1.4 million deletions per second.