20 results for “SiGe BiCMOS”
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A 140-GHz transmitter with direct raised-cosine-like envelope shaping and wide-range phase tuning is presented in 90-nm SiGe BiCMOS, achieving up to 8 Gbpers data rate, 34-dB sidelobe suppression, 22.…
The paper presents SABLE, an NDA-safe framework that allows large language models to optimize analog circuits in industrial EDA tools while protecting proprietary information.
The paper introduces a design-oriented methodology and a closed-form macromodel to quantify how noise coupled through Through-Silicon Vias (TSVs) degrades the spectral purity of sensitive RF oscillato…
SangHoon Cha, Jaewan Choi, Byeongho Kim, Yoonah Paik +2 more
This paper introduces a high-fidelity, integrated hardware-software simulator for LPDDR5X-PIM, enabling precise evaluation of system performance and energy efficiency.
This paper presents an open-source tool for generating efficient hardware parsers from high-level specifications using a decoupled parsing intermediate representation and custom symbolic tokens.
Xi Yang, Taolue Chen, Yuqi Chen, Fu Song +2 more
This paper introduces a novel algorithm, CiSC, to efficiently and optimally synthesize circuit implementations of linear codes for hardware security, significantly outperforming existing state-of-the-…
NEMESIS is a framework that uses large language models to generate accurate performance equations for operational transconductance amplifiers (OTAs) with a balance between speed and accuracy.
This paper presents the SiLIF-DBS controller, a low-power neuromorphic silicon neuron stimulator for adaptive deep brain stimulation (aDBS) of Parkinson's disease, achieving strong beta suppression wi…
This paper proposes a new approach for real-time, dynamic and sound quantization and hardware to support it for resource-efficient neural networks and high-precision mathematics on edge devices, ensur…
The paper introduces a novel toolkit to enhance RISC-V Trusted Execution Environments (TEEs) by adding modular extensions for secure enclave update, migration, state continuity, and trusted time, ther…
This paper presents a product coding scheme that converts bit-level reliability into block-level reliability, achieving the same asymptotic rate.
This paper presents hardware-faithful verification for IEC 61131-3 on low-cost microcontrollers, reducing false alarms and preserving robustness proofs.
The paper introduces a physics-informed active learning framework to optimize GaN tri-gate FinFETs for vertical power delivery, identifying a multi-fin device (D1) that significantly outperforms a sin…
Elie Bursztein, Michael Gruber, Karel Král, Jean-Michel Picod +2 more
This paper proposes training a single neural network using EM traces collected from multiple probe positions to detect cryptographic leakage across a larger area of a target device, validated by cross…
The paper proposes a Ferroelectric Charge-Domain Compute Cell (FCDC) using HZO memcapacitors to perform attention computation, achieving significant energy efficiency gains, especially for long-reside…
The paper introduces a four-stage structural dependency analysis hierarchy that enables scalable, sound first-order masking verification for large, production-level post-quantum cryptographic accelera…
The paper demonstrates that the Brazilian e-Voting Machine interface generates a simple and highly distinctive electromagnetic spectral signature, raising significant concerns about its susceptibility…
The paper demonstrates that for FFT-based radar imaging on Apple Silicon, the limiting factor for half-precision (FP16) is dynamic range, not mantissa precision, and proposes a block-floating-point (B…