A new HLS tool is presented that enables fine-grained pipeline control in a sequential programming model for competitive PPA.

HighTide is an evolving, AI-assisted, open-source benchmark suite for VLSI design, providing a comprehensive and scalable platform for hardware development.

StepPRM-RTL is a novel framework that enhances LLM-based RTL code generation for digital hardware designs.

Introduce Parallel-Synthesis, a framework enabling a synthesizer to directly consume parallel agent branches' KV caches, improving efficiency and performance.

The paper introduces VHDLSuite, an infrastructure for evaluating Large Language Models in VHDL, including a data pipeline, benchmark, and evaluation framework.

This paper presents an open-source tool for generating efficient hardware parsers from high-level specifications using a decoupled parsing intermediate representation and custom symbolic tokens.

The paper introduces ProofLoop, a novel ReAct agent that uses a solver-in-the-loop approach to automatically generate and formally verify SystemVerilog Assertions (SVA) from natural language specifica…

The paper introduces two library combinators, prune and defrel/bank, to bring observational deduplication and bottom-up enumeration into the relational setting using plain miniKanren.

The paper introduces Atomic Decomposition and Recombination (ADR), a novel framework that generates genuinely novel and challenging verifiable code tasks, significantly improving the scalability of Re…

The paper introduces DOMINO, a novel inductive framework that synthesizes domain-specific data for LLMs using only reference examples, significantly improving performance on challenging, implicitly de…

This paper presents ADAC, a compiler that converts trained differentiable audio models into efficient FAUST code for real-time audio effects.

The paper proposes MaskedHLSVerif, a novel formal verification toolflow that accurately verifies the Power Side Channel Attack (PSCA) security of masked hardware generated by High Level Synthesis (HLS…

The paper introduces StreamSynth, a sequential setting for synthetic data generation, and proposes SynLearner, a framework that enables LLMs to improve synthesis performance by accumulating and transf…

The paper introduces SchGen, the first large language model capable of generating editable PCB schematics from natural language by using a novel semantically grounded code representation.

This paper introduces MultModLM, a benchmark for evaluating Large Language Models on generating hardware schematics from RTL descriptions, and identifies limitations and unreliability of LLM-as-a-judg…

The paper proposes a visual program synthesis framework using a VLM to generate accurate training data for semiconductor inspection, mitigating the sim-to-real gap by applying input binarization to st…

pcbGPT is a grounded system that automatically generates editable KiCad PCB schematics from natural language requirements, achieving high accuracy on complex embedded design tasks.