Johann Knechtel

VeriCWEty proposes an embedding-based framework to detect and classify common software vulnerabilities (CWEs) in Verilog RTL code at both module and line levels, achieving high detection accuracy.

The paper introduces HarmChip, a novel benchmark to evaluate LLM vulnerability to domain-specific hardware security threats, revealing that current safety guardrails fail against semantically disguised attacks.

This review analyzes the dual impact of integrating Large Language Models (LLMs) into hardware design, detailing both their transformative potential in EDA and the critical security vulnerabilities they introduce.

The paper expands a logic locking interface with additional encoded inputs and identifies vulnerabilities in two realizations, showing that the without-ES variant does not provide additional brute-force dimensions and the with-ES variant is vulnerable to polynomial-time white-box attacks.