Sujan Kumar Saha
2 indexed papers
Recent (6 mo)
2With code
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0Publications per year
226
Top categories
Crypto×2
Frequent co-authors
Research Timeline
2026
Assertain: Automated Security Assertion Generation Using Large Language Models
Assertain is an automated framework that uses large language models and design analysis to generate high-quality, executable security assertions for hardware designs, significantly outperforming state-of-the-art models like GPT-5.
Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
This paper surveys the use of hardware emulation for security verification in System-on-Chip (SoC) design, positioning emulation as a critical, high-fidelity pre-silicon assurance technology.
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Papers
cs.CRRecentApr 16, 2026
Emulation-based System-on-Chip Security Verification: Challenges and Opportunities
This paper surveys the use of hardware emulation for security verification in System-on-Chip (SoC) design, positioning emulation as a critical, high-fidelity pre-silicon assurance technology.
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cs.CRRecentApr 2, 2026