The paper introduces Chimera, a highly efficient and scalable MCU designed for ultra-low-power edge AI inference, achieving 3.1 TOPS/W by integrating a dedicated transformer accelerator and a QoS-guar…

The paper presents ExaGEMM, a framework for designing and exploring CPU-native low-bit GEMM via register-resident LUT execution.

This paper compares three neuromorphic core designs for handling weight sparsity in event-driven neural networks and quantifies the performance and energy costs.

The paper proposes a framework to harvest unused computation resources on AI chips for general-purpose tasks using neural architecture search and approximation techniques.

Valinor is a hardware-OS cooperative memory allocation substrate that introduces a programmable hardware allocation engine for improving performance and reducing energy consumption in virtual-to-physi…

This paper introduces BigPower, a hierarchical source-level surrogate model for fine-grained module-level power estimation during CPU design using large language models and architectural hierarchy.

A new HLS tool is presented that enables fine-grained pipeline control in a sequential programming model for competitive PPA.

Physical AI inference (batch-1 decode) is primarily memory-bandwidth-bound, but the observed latency gap between fast and slow GPUs is not solely due to memory bandwidth, as launch-side overheads beco…

This paper proposes a lightweight architectural enhancement for FPGA designs to improve data movement between block RAMs and digital signal processing units for deep learning workloads, incurring negl…

A co-designed hardware-software approach for task-conditional sparsity in multi-task inference models, reducing FLOPs, latency, and energy.

PolyQ is a compiler/quantization co-design for activation-aware channel-wise bit allocation on CPUs, providing stable quality scaling and energy efficiency for fine-grained fractional-bit CPU deployme…

This paper characterizes per-bit-position fault sensitivity in machine learning inference across various workloads and floating-point formats, identifying a sharp bit-sensitivity transition and derivi…

HighTide is an evolving, AI-assisted, open-source benchmark suite for VLSI design, providing a comprehensive and scalable platform for hardware development.

This paper presents an open-source tool for generating efficient hardware parsers from high-level specifications using a decoupled parsing intermediate representation and custom symbolic tokens.

This paper addresses the obstacles of using Crossbar-based In-Memory Processing (IMP) accelerators for deep neural networks (DNNs) by reusing bit-shift units for multiplication, applying pruning metho…

The paper introduces a novel hardware aging attack that exploits the commutative properties of addition to induce unbalanced stress on AI accelerator transistors, significantly degrading model accurac…