This paper presents two loop cache architectures for RISC-V processors to reduce instruction fetches and energy consumption during AI inference.

The paper introduces a novel toolkit to enhance RISC-V Trusted Execution Environments (TEEs) by adding modular extensions for secure enclave update, migration, state continuity, and trusted time, ther…

VeriCWEty proposes an embedding-based framework to detect and classify common software vulnerabilities (CWEs) in Verilog RTL code at both module and line levels, achieving high detection accuracy.

The paper introduces Heimdall, an automated pipeline that uses LLMs and formal verification to safely and automatically migrate legacy, potentially buggy eBPF programs written in C to memory-safe Rust…

KoAT is a tool that automatically infers complexity bounds and proves termination of integer programs using an alternating modular analysis approach and a portfolio of techniques.

Elevator is a novel, deterministic binary translator that statically translates entire x86-64 executables to AArch64 by considering all possible interpretations of every byte, eliminating the need for…

The paper introduces Kops, an extension interface for eBPF that allows userspace compilers and kernel modules to introduce new operations without modifying the kernel core, improving performance and r…

This paper presents CopilotVerifier, a tool that generates proofs of correctness for the compiled output of the Copilot runtime verification framework.

This paper presents a novel approach for constructing information flow paths from RTL trace data for automated property generation and validation in hardware design.

A new HLS tool is presented that enables fine-grained pipeline control in a sequential programming model for competitive PPA.

Branch Landing (BRL) is a novel forward-edge CFI framework for RISC-V that uses Bloom filters to overcome the source authorization limitations of existing hardware CFI, achieving low overhead for fine…

NeuroLog is a novel, build-free neuro-symbolic pipeline that combines LLM-derived dataflow facts, Datalog, and SMT solving to systematically discover and synthesize exploitable memory safety vulnerabi…

The largest reported verification campaign for the Rust standard library is presented, integrating complementary tools and analyzing effectiveness.

PoisonCap introduces a new 'poison' capability format for CHERI systems to provide efficient, strict use-after-free and initialization safety, surpassing existing temporal safety solutions.

This paper introduces InvWeaver, a neuro-symbolic framework for synthesizing loop invariants in programs with multiple interacting loops.

The paper introduces BOUNDARY FLOW, an LLVM-based framework that enhances kernel fuzzing and analysis by extracting per-task, state-aware data-flow information (arguments and return values) at functio…

This paper demonstrates a software-only attack chain on EPYC Milan that extracts the hardware root seed, thereby undermining the security guarantees of AMD's SEV-SNP by allowing the forging of valid a…

The paper introduces a novel multi-LLM orchestration system combined with symbolic execution to successfully detect memory vulnerabilities in uncompilable, incomplete Rust CVE code snippets, achieving…