OpenEye is a scalable, sparsity-aware FPGA-based hardware accelerator designed to efficiently execute common deep neural network operations, demonstrating favorable performance-resource trade-offs acr…

This paper presents FlexViT, a reconfigurable FPGA accelerator for efficient Vision Transformer (ViT) inference on edge devices, achieving up to 2.74x speedup on accelerator-executed layers.

This paper proposes a lightweight architectural enhancement for FPGA designs to improve data movement between block RAMs and digital signal processing units for deep learning workloads, incurring negl…

This paper introduces Mega, a digital architecture for Convolutional Spiking Neural Networks (SNNs) that addresses underutilization of parallelism and inflexibility in existing SNN accelerators throug…

This paper presents a hardware-oriented description of GoldenFloat, a static-split floating-point family, and its concrete artefacts.

This paper presents an open-source tool for generating efficient hardware parsers from high-level specifications using a decoupled parsing intermediate representation and custom symbolic tokens.

The paper introduces BLADEI, a hardware-accelerated framework that screens FPGA configuration bitstreams for anomalies in real-time, overcoming the latency bottleneck of traditional software-based det…

O-POPE is a novel outer-product engine that accelerates floating-point GEMM by repurposing FPU pipeline registers as buffers, achieving high utilization and improved energy efficiency.

The paper implements and evaluates several hardware priority queue architectures on modern FPGA platforms and provides a quantitative analysis.

The paper proposes a hybrid ASIC+eFPGA architecture to enhance the security and resilience of edge LLM inference accelerators against both runtime and supply-chain attacks.

This paper proposes a resource-oriented one-shot quantiser pruning method for high granularity quantisation (HGQ) to reduce search cost and achieve a competitive Pareto frontier in FPGA-based edge neu…