This paper presents an open-source tool for generating efficient hardware parsers from high-level specifications using a decoupled parsing intermediate representation and custom symbolic tokens.

This paper proposes a lightweight architectural enhancement for FPGA designs to improve data movement between block RAMs and digital signal processing units for deep learning workloads, incurring negl…

The paper introduces BLADEI, a hardware-accelerated framework that screens FPGA configuration bitstreams for anomalies in real-time, overcoming the latency bottleneck of traditional software-based det…

This paper presents a hardware-oriented description of GoldenFloat, a static-split floating-point family, and its concrete artefacts.

This paper enhances open-source FPGA CAD tools to model and explore inter-die routing architectures for 2.5D and 3D FPGAs, demonstrating that these architectures can significantly improve performance…

The paper implements and evaluates several hardware priority queue architectures on modern FPGA platforms and provides a quantitative analysis.

This paper proposes a new approach for real-time, dynamic and sound quantization and hardware to support it for resource-efficient neural networks and high-precision mathematics on edge devices, ensur…

The paper proposes MaskedHLSVerif, a novel formal verification toolflow that accurately verifies the Power Side Channel Attack (PSCA) security of masked hardware generated by High Level Synthesis (HLS…

This survey reviews the integration of AI and LLMs into hardware security verification, demonstrating its potential to automate complex stages while stressing the necessity of grounding AI outputs in…

A new HLS tool is presented that enables fine-grained pipeline control in a sequential programming model for competitive PPA.

The paper proposes a hybrid ASIC+eFPGA architecture to enhance the security and resilience of edge LLM inference accelerators against both runtime and supply-chain attacks.

The paper proposes a highly reconfigurable 256x128 in-memory computing array that significantly improves efficiency and performance for analog computing by introducing novel components for ADC, weight…