A new HLS tool is presented that enables fine-grained pipeline control in a sequential programming model for competitive PPA.

StepPRM-RTL is a novel framework that enhances LLM-based RTL code generation for digital hardware designs.

The paper proposes MaskedHLSVerif, a novel formal verification toolflow that accurately verifies the Power Side Channel Attack (PSCA) security of masked hardware generated by High Level Synthesis (HLS…

HighTide is an evolving, AI-assisted, open-source benchmark suite for VLSI design, providing a comprehensive and scalable platform for hardware development.

The paper introduces ProofLoop, a novel ReAct agent that uses a solver-in-the-loop approach to automatically generate and formally verify SystemVerilog Assertions (SVA) from natural language specifica…

The paper introduces VHDLSuite, an infrastructure for evaluating Large Language Models in VHDL, including a data pipeline, benchmark, and evaluation framework.

This paper presents an open-source tool for generating efficient hardware parsers from high-level specifications using a decoupled parsing intermediate representation and custom symbolic tokens.

This paper introduces MultModLM, a benchmark for evaluating Large Language Models on generating hardware schematics from RTL descriptions, and identifies limitations and unreliability of LLM-as-a-judg…

The paper introduces Atomic Decomposition and Recombination (ADR), a novel framework that generates genuinely novel and challenging verifiable code tasks, significantly improving the scalability of Re…

The paper introduces two library combinators, prune and defrel/bank, to bring observational deduplication and bottom-up enumeration into the relational setting using plain miniKanren.

The paper introduces SchGen, the first large language model capable of generating editable PCB schematics from natural language by using a novel semantically grounded code representation.

Introduce Parallel-Synthesis, a framework enabling a synthesizer to directly consume parallel agent branches' KV caches, improving efficiency and performance.

The paper proposes using an LLM aggregator that analyzes complete reasoning traces, demonstrating that trace-level synthesis is superior to traditional consensus methods like majority voting for solvi…

This review analyzes the dual impact of integrating Large Language Models (LLMs) into hardware design, detailing both their transformative potential in EDA and the critical security vulnerabilities th…

This paper introduces InvWeaver, a neuro-symbolic framework for synthesizing loop invariants in programs with multiple interacting loops.

This paper presents ADAC, a compiler that converts trained differentiable audio models into efficient FAUST code for real-time audio effects.

The paper analyzes a fragment of Higher-Order Datalog, showing that restricting recursion to a linear form shifts its expressive power from time complexity to space complexity, specifically capturing…