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20 results for “Intelligence Processing Unit”

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cs.ARcs.AIcs.ETEmpiricalRecentJul 24, 2026

Multi-primitive in-memory computing for Monte Carlo tree search

Tergel Molom-Ochir, Benjamin F. Morris, Yintao He, Archit Gajjar +5 more

This paper introduces phase-to-primitive decomposition to enable Monte Carlo tree search (MCTS) on in-memory computing (IMC) systems, achieving significant energy efficiency and performance improvemen…

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cs.GRcs.CVcs.DCEmpiricalRecentJul 17, 2026

Rendering 3D Gaussians on a Graph Processor

Nicholas Fry, Ignacio Alzugaray, Mark Pupilli, Paul H. J. Kelly +1 more

First implementation of a 3D Gaussian renderer on an Intelligence Processing Unit (IPU) with 1,472 independent tiles using only on-chip SRAM.

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cs.CRRecentApr 25, 2026

Core Logic and Algorithmic Performance Enhancements for a System Vulnerability Analysis Technique for Complex Mission Critical Systems Implementation

Matthew Tassava, Cameron Kolodjski, Jordan Milbrath, Jeremy Straub

The paper details significant enhancements to the SONARR system's core logic, replacing restrictive Boolean logic with generic data type support and adding multi-compute capabilities to improve vulner…

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cs.ARcs.LGEmpiricalRecentJun 28, 2026

Harvesting AI Computation at the Edge via Generic Approximation

Yihan Wang, Huiru Yan, Luxin Zhang, Long Cheng +5 more

The paper proposes a framework to harvest unused computation resources on AI chips for general-purpose tasks using neural architecture search and approximation techniques.

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cs.CRcs.AIRecentMar 17, 2026

Deep learning based intelligent IDS for Large-scale IoT networks

Isha Andrade, Shalaka S Mahadik, Mithun Mukherjee, Pranav M Pawar +1 more

This paper proposes and evaluates two lightweight deep learning-based intelligent Intrusion Detection Systems (CNN and LSTM) to enhance the security of large-scale IoT networks, achieving high classif…

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cs.CRcs.AIcs.LGRecentMay 21, 2026

Characterizing the Fault Response of the Intel Neural Compute Stick 2 Under Single-Pulse Electromagnetic Fault Injection

Štefan Kučerák, Jakub Breier, Xiaolu Hou

The paper systematically characterizes the fault response of the Intel NCS2 accelerator to electromagnetic fault injection, revealing a major degradation mode that is undetectable by standard inferenc…

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cs.LGcs.AREmpiricalRecentJun 16, 2026

Reconfigurable Computing Challenge: Transformer for Jet Tagging on Versal AI Engines

Gram Koski, Sean Lipps, Zhenghua Ma, G. Abarajithan +1 more

The paper presents an initial implementation of a quantized, integer-only transformer for jet tagging on the AMD Versal AI Engine using a reusable software framework.

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cs.CRRecentMay 13, 2026

HE-PIM: Demystifying Homomorphic Operations on a Real-world Processing-in-Memory System

Harshita Gupta, Mayank Kabra, Jaewoo Park, Priyam Mehta +8 more

The paper characterizes Homomorphic Encryption (HE) operations on a real-world Processing-In-Memory (PIM) system, demonstrating that while PIM is a viable alternative to CPUs/GPUs, performance is limi…

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cs.CRcs.AIcs.NIRecentMar 26, 2026

Sovereign AI at the Front Door of Care: A Physically Unidirectional Architecture for Secure Clinical Intelligence

Vasu Srinivasan, Dhriti Vasu

The paper proposes a Sovereign AI architecture for clinical triage that ensures maximum security by performing all inference on-device and receiving data only through physically unidirectional channel…

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cs.PFcs.ARcs.DCRecentMay 27, 2026

Rotary GPU: Exploring Local Execution Paths for Large Mixture-of-Experts Models Under Limited GPU Memory

Myeong Jun Jo

The paper introduces Rotary GPU, an exploratory execution approach demonstrating that large Mixture-of-Experts models can be run locally on consumer GPUs with limited VRAM, achieving usable decode thr…

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cs.AREmpiricalRecentJun 10, 2026

BenDi: An Energy-Efficient Quasi-Stochastic Systolic Architecture for Edge Bioelectronics

Bochen Ye, Yihan Pan, Shady Agwa, Themis Prodromakis

This paper presents BenDi, an energy-efficient quasi-stochastic systolic architecture for bioelectronic systems on the edge.

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cs.CRcs.AIcs.CYRecentApr 13, 2026

Hardening x402: PII-Safe Agentic Payments via Pre-Execution Metadata Filtering

Vladimir Stantchev

The paper introduces presidio-hardened-x402, an open-source middleware that intercepts x402 payment requests to detect and redact PII and enforce spending policies before on-chain settlement.

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cs.CVcs.CRcs.LGRecentMay 7, 2026

Smart Railway Obstruction Detection System using IoT and Computer Vision

Pravin Kumar, Mritunjay Shall Peelam, Ramakant Kumar, Sanjay Kumar +1 more

The paper proposes NETRA, a cost-effective, internet-independent system using probabilistic sensor fusion and edge-AI classification on Raspberry Pi platforms to achieve high-accuracy, real-time detec…

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cs.AREmpiricalRecentJul 17, 2026

From Patterns to Parsers: Automatic Generation of Efficient Hardware Parsers for FPGAs

Tushar Garg, Andrew Boutros

This paper presents an open-source tool for generating efficient hardware parsers from high-level specifications using a decoupled parsing intermediate representation and custom symbolic tokens.

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cs.SDcs.AIEmpiricalRecentJul 21, 2026

What the Waveform Knows: Transparent-first Speech and Audio Intelligence with Caption Studio

Cheng Siong Chin, Jianhua Zhang, Mohan Venkateshkumar

Caption Studio is a transparency-first speech and audio intelligence platform that provides automated transcription, speaker diarization, speech analytics, signal-level audio analysis, and subtitle ge…

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cs.DCcs.PFEmpiricalRecentJul 23, 2026

PRISM: Evaluating POSIX Storage Systems for AI Research Workflows

Adithya Kumar, Aditya Basu, Jacob Kahn, Parth Malani +2 more

The paper introduces PRISM, an evaluation framework for assessing POSIX storage systems for AI research workloads, and compares Lustre and NFS based systems.

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cs.OScs.CREmpiricalRecentJun 23, 2026

Kops: Safely Extending the eBPF Compilation Pipeline with Native Operations

Yusheng Zheng, Zhengjie Ji, Weichen Tao, Hao Sun +3 more

The paper introduces Kops, an extension interface for eBPF that allows userspace compilers and kernel modules to introduce new operations without modifying the kernel core, improving performance and r…

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