HighTide is an evolving, AI-assisted, open-source benchmark suite for VLSI design, providing a comprehensive and scalable platform for hardware development.

This paper presents CoEvoP&R, a framework that uses a large language model to automatically evolve analytical placement objectives, reducing post-route routed wirelength, congestion, and improving tim…

This paper introduces PDAGENT-BENCH, a comprehensive benchmark for evaluating Large Language Models and vision-language models in the physical design stack of Very Large-Scale Integrated Circuits.

This review analyzes the dual impact of integrating Large Language Models (LLMs) into hardware design, detailing both their transformative potential in EDA and the critical security vulnerabilities th…

This paper presents an open-source tool for generating efficient hardware parsers from high-level specifications using a decoupled parsing intermediate representation and custom symbolic tokens.

This paper presents AlphaRoute, a multi-objective adaptive search framework for VLSI global routing using Large Language Models as semantic policy optimizers.

This paper discusses the potential of Large Language Models (LLMs) in Electronic Design Automation (EDA) and reviews their applications in tasks such as circuit and testbench generation, design qualit…

The paper introduces SchGen, the first large language model capable of generating editable PCB schematics from natural language by using a novel semantically grounded code representation.

FT-Pilot is a novel GNN-guided LLM framework that automatically rewrites RTL code to harden digital circuits against soft errors, providing an efficient, automated path for reliability optimization.

A new HLS tool is presented that enables fine-grained pipeline control in a sequential programming model for competitive PPA.

The paper introduces CASS-RTL, a novel, model-agnostic framework that enhances the functional correctness of Large Language Models (LLMs) generating Register-Transfer Level (RTL) code by leveraging th…

This paper introduces MultModLM, a benchmark for evaluating Large Language Models on generating hardware schematics from RTL descriptions, and identifies limitations and unreliability of LLM-as-a-judg…

This paper introduces BigPower, a hierarchical source-level surrogate model for fine-grained module-level power estimation during CPU design using large language models and architectural hierarchy.

This paper evaluates AI agent systems for electronic design automation (EDA) using a unified benchmark called FluxBench, assessing their performance across various EDA workflows and tasks.

This paper proposes a lightweight architectural enhancement for FPGA designs to improve data movement between block RAMs and digital signal processing units for deep learning workloads, incurring negl…

StepPRM-RTL is a novel framework that enhances LLM-based RTL code generation for digital hardware designs.

The paper implements and evaluates several hardware priority queue architectures on modern FPGA platforms and provides a quantitative analysis.

NEMESIS is a framework that uses large language models to generate accurate performance equations for operational transconductance amplifiers (OTAs) with a balance between speed and accuracy.