The first formal verification of an out-of-order multiprocessor against an in-order, weak-memory ISA using a core specification and mechanized proofs in Rocq.

QCIVET introduces a novel contract-based framework to ensure the integrity of hybrid quantum-classical pipelines by verifying both the structure (syntactic) and the behavior (semantic) of quantum stag…

This paper introduces HiFuzz, a hierarchical reinforcement learning framework for processor verification that replaces mutation with a structured generation process and integrates coverage reward mech…

This paper proposes a method for verifying functional correctness of message-passing concurrent programs using Constrained Horn Clause (CHC) solving.

This survey reviews the integration of AI and LLMs into hardware security verification, demonstrating its potential to automate complex stages while stressing the necessity of grounding AI outputs in…

The paper introduces HPCCFA, a novel mechanism that leverages Hardware Performance Counters (HPCs) to provide hardware-backed Control Flow Attestation (CFA) on commodity CPUs, thereby enhancing the se…

The paper introduces Kops, an extension interface for eBPF that allows userspace compilers and kernel modules to introduce new operations without modifying the kernel core, improving performance and r…

This paper surveys the use of hardware emulation for security verification in System-on-Chip (SoC) design, positioning emulation as a critical, high-fidelity pre-silicon assurance technology.

The paper proposes a federated formal verification architecture that treats verification as a polyglot proof system, successfully validating it on complex production subsystems like a Raft consensus m…

The paper proposes using hardware fingerprints instead of vulnerable cryptographic keys to enhance the security and robustness of GPU location verification for governing advanced AI development.

The paper develops a novel, sound, and complete deductive proof system for proving contract satisfaction, which is crucial for verifying CPU security against side-channel attacks.

Assertain is an automated framework that uses large language models and design analysis to generate high-quality, executable security assertions for hardware designs, significantly outperforming state…

This paper presents a novel approach for constructing information flow paths from RTL trace data for automated property generation and validation in hardware design.

The paper proposes a method for bit-exact verification of AI inference outputs without sacrificing performance, demonstrating that deterministic, precise re-computation is possible even across differe…

The paper proposes HammerWatch, a novel remote attestation protocol that enables external verifiers to detect hardware-induced disturbances, specifically Rowhammer-like attacks, by analyzing memory-le…

This paper proposes a new approach for real-time, dynamic and sound quantization and hardware to support it for resource-efficient neural networks and high-precision mathematics on edge devices, ensur…

The paper introduces the Reconstructive Authority Model (RAM), a novel framework that proves execution validity by assessing state coverage rather than just state integrity, showing that existing atte…

This paper introduces BigPower, a hierarchical source-level surrogate model for fine-grained module-level power estimation during CPU design using large language models and architectural hierarchy.

The paper introduces SymTEE, an LLM-assisted symbolic execution framework that detects missing input validation vulnerabilities in TEE applications without needing complex, real TEE setups.