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20 results for “reconfigurable platform”

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cs.DCEmpiricalRecentJul 21, 2026

A User-oriented Portable, Reproducible, and Scalable Software Ecosystem

Alfio Lazzaro, Utz-Uwe Haus, Sandrine Charousset, Nina Mujkanovic

This paper presents a software ecosystem enabling consistent development environments for running workflows across diverse hardware platforms.

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cs.ARcs.AIEmpiricalRecentJun 26, 2026

Agentic Hardware Design as Repository-Level Code Evolution

Cunxi Yu, Chenhui Deng, Nathaniel Pinckney, Brucek Khailany

The paper introduces HORIZON, a self-evolving agent framework for hardware design using git operations.

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cs.LGcs.AREmpiricalRecentJun 16, 2026

Reconfigurable Computing Challenge: Transformer for Jet Tagging on Versal AI Engines

Gram Koski, Sean Lipps, Zhenghua Ma, G. Abarajithan +1 more

The paper presents an initial implementation of a quantized, integer-only transformer for jet tagging on the AMD Versal AI Engine using a reusable software framework.

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cs.CRcs.ETRecentMay 9, 2026

Hardware-Accelerated Line-Rate Bitstream Screening for Secure FPGA Reconfiguration

Rye Stahle-Smith, Carter Antley, Jason D. Bakos, Rasha Karakchi

The paper introduces BLADEI, a hardware-accelerated framework that screens FPGA configuration bitstreams for anomalies in real-time, overcoming the latency bottleneck of traditional software-based det…

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cs.ARRecentJun 1, 2026

CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees

Lorenzo Leone, Philip Wiese, Gamze İslamoğlu, Michael Rogenmoser +3 more

The paper introduces Chimera, a highly efficient and scalable MCU designed for ultra-low-power edge AI inference, achieving 3.1 TOPS/W by integrating a dedicated transformer accelerator and a QoS-guar…

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cs.AREmpiricalRecentJul 16, 2026

Valinor: Architectural Support for Fast, Energy-Efficient and Programmable Physical Memory Allocation

Konstantinos Kanellopoulos, Spiros Galanopoulos, Konstantinos Sgouras, Vlad-Petru Nitu +6 more

Valinor is a hardware-OS cooperative memory allocation substrate that introduces a programmable hardware allocation engine for improving performance and reducing energy consumption in virtual-to-physi…

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cs.ITSurveyRecentJun 10, 2026

Reconfigurable Antennas for Next-generation Mobile Communication Networks: A Comprehensive Survey and Tutorial

Yizhe Zhao, Long Zhang, Halvin Yang, Kun Yang +3 more

This paper presents a comprehensive survey on reconfigurable antennas for next-generation mobile networks, focusing on their potential and applications.

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cs.ARRecentMay 29, 2026

A Reconfigurable Computing In-Memory Macro with Charge-sharing-based Weighted Accumulator

Junyi Yang, Shuai Dong, Zhengnan Fu, Hongyang Shang +1 more

The paper proposes a highly reconfigurable 256x128 in-memory computing array that significantly improves efficiency and performance for analog computing by introducing novel components for ADC, weight…

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cs.AREmpiricalRecentJul 17, 2026

From Patterns to Parsers: Automatic Generation of Efficient Hardware Parsers for FPGAs

Tushar Garg, Andrew Boutros

This paper presents an open-source tool for generating efficient hardware parsers from high-level specifications using a decoupled parsing intermediate representation and custom symbolic tokens.

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cs.HCcs.AIRecentMay 31, 2026

pcbGPT: Automatic PCB Schematic Synthesis from Natural Language Requirements

Tobias King, Steven Kehrberg, Michael Beigl, Tobias Röddiger

pcbGPT is a grounded system that automatically generates editable KiCad PCB schematics from natural language requirements, achieving high accuracy on complex embedded design tasks.

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cs.ARcs.CVcs.DCEmpiricalRecentJun 30, 2026

FlexViT: A Flexible FPGA-based Accelerator for Edge Vision Transformers

Hubert Dymarkowski, Xingjian Fu, Rappy Saha, Jude Haris +1 more

This paper presents FlexViT, a reconfigurable FPGA accelerator for efficient Vision Transformer (ViT) inference on edge devices, achieving up to 2.74x speedup on accelerator-executed layers.

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cs.AREmpiricalRecentJul 7, 2026

Boosting FPGA Performance with Direct BRAM-DSP Paths

Jiajun Hu, Ruthwik Reddy Sunketa, Andrew Boutros, Aman Arora

This paper proposes a lightweight architectural enhancement for FPGA designs to improve data movement between block RAMs and digital signal processing units for deep learning workloads, incurring negl…

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cs.DCcs.SEEmpiricalRecentJul 28, 2026

WASP: A Configurable Framework for Portable Stateful Serverless Applications

Matteo Cenzato, Dario d'Abate, Arianna Dragoni, Giacomo Orsenigo +2 more

WASP is a configurable framework for stateful serverless execution on the edge-cloud continuum, allowing swapping of runtimes, datastores, and policies.

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eess.SPcs.AIRecentMay 27, 2026

Project SPARROW and the Future of Conservation Technology

Juan M. Lavista Ferres, Carl Chalmers, Bruno Demuro Segundo, Zhongqi Miao +13 more

The paper introduces SPARROW, an autonomous, open-source platform that uses solar power, edge AI, and satellite communication to enable continuous, scalable biodiversity monitoring in remote global ec…

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cs.ARcs.AIcs.LGEmpiricalRecentJun 11, 2026

VHDLSuite: Unified Pipeline for LLM VHDL Generation with Data Synthesis and Evaluation

Yijun Shen, Minghao Shao, Yichen Zhao, Zhuoyan Yu +3 more

The paper introduces VHDLSuite, an infrastructure for evaluating Large Language Models in VHDL, including a data pipeline, benchmark, and evaluation framework.

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