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~ similar to 2604.15249v2· 20 results

cs.CRRecentApr 20, 2026

From Finite Enumeration to Universal Proof: Ring-Theoretic Foundations for PQC Hardware Masking Verification

Ray Iskander, Khaled Kirah

The paper provides the first machine-checked universal proof, using ring theory, that value-independence implies identical marginal distributions for arithmetic masking, thereby extending the verifica…

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cs.CRRecentApr 22, 2026

Fresh Masking Makes NTT Pipelines Composable: Machine-Checked Proofs for Arithmetic Masking in PQC Hardware

Ray Iskander, Khaled Kirah

The paper provides machine-checked proofs demonstrating that fresh per-stage arithmetic masking ensures pipeline-level security for Number Theoretic Transform (NTT) accelerators used in Post-Quantum C…

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cs.CRRecentApr 4, 2026

Partial Number Theoretic Transform Masking in Post-Quantum Cryptography (PQC) Hardware: A Security Margin Analysis

Ray Iskander, Khaled Kirah

The paper analyzes the security of a partially masked hardware accelerator for Number Theoretic Transform (NTT) in PQC, demonstrating that the claimed security margins are significantly overestimated…

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cs.CRRecentMay 4, 2026

The 1-Bit Barrier is Universal: k-Stage Pipeline Composition and Unified Leakage Bounds for Standard Modular Reductions in PQC Hardware

Ray Iskander, Khaled Kirah

This paper proves that the per-observation leakage bound for deep, multi-stage masked Number Theoretic Transform (NTT) pipelines remains constant and low ($2/q$), regardless of the pipeline's depth ($…

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cs.CRcs.ARcs.PFRecentMar 19, 2026

Benchmarking NIST-Standardised ML-KEM and ML-DSA on ARM Cortex-M0+: Performance, Memory, and Energy on the RP2040

Rojin Chhetri

This paper provides the first systematic, isolated benchmarks of NIST-standardized post-quantum cryptography (ML-KEM and ML-DSA) on the highly constrained ARM Cortex-M0+ processor, showing performance…

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cs.CRRecentMar 19, 2026

Controller Datapath Aware Verification of Masked Hardware Generated via High Level Synthesis

Nilotpola Sarma, Vaishali Ghanshyam Chaudhuri, Chandan Karfa

The paper proposes MaskedHLSVerif, a novel formal verification toolflow that accurately verifies the Power Side Channel Attack (PSCA) security of masked hardware generated by High Level Synthesis (HLS…

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quant-phcs.CRRecentApr 29, 2026

A Multi-Level Integrity Evaluation Framework for Quantum Circuits under Controlled Anomaly Injection

Ejaz Ahmed, Boshuai Ye, Syed Hamza Shah, Muhammad Azeem Akbar +1 more

The paper proposes a novel three-layer metric framework to comprehensively evaluate quantum circuit integrity by combining structural, operational, and interaction-level analyses, demonstrating that n…

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cs.CRRecentApr 27, 2026

Machine-Checked Cardinality Bounds for Masked Barrett Reduction: A 1-Bit Side-Channel Leakage Barrier in Post-Quantum Cryptographic Hardware

Ray Iskander, Khaled Kirah

The paper establishes a universal, machine-checked 1-Bit Barrier for the internal wire map of masked Barrett reduction, providing a strong side-channel leakage bound for post-quantum cryptography.

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cs.CRRecentApr 28, 2026

Prime-Field PINI: Machine-Checked Composition Theorems for Post-Quantum NTT Masking

Ray Iskander, Khaled Kirah

The paper establishes the first machine-checked composition theorems for arithmetic masking over prime fields, demonstrating that fresh random masking between pipeline stages completely erases securit…

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cs.CRcs.CLRecentApr 28, 2026

The Surprising Universality of LLM Outputs: A Real-Time Verification Primitive

Alex Bogdan, Adrian de Valois-Franklin

The paper identifies a universal, statistically predictable distribution (Mandelbrot) governing LLM outputs, enabling a highly efficient, model-agnostic scoring primitive for provenance and quality as…

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cs.CRquant-phRecentMay 16, 2026

quantum-safe: Bridging the Post-Quantum Production Gap with a Hybrid-by-Default Python Cryptography Library

Animesh Shaw

The paper introduces 'quantum-safe,' a Python library that addresses the remaining 'production gap' in post-quantum cryptography (PQC) by providing robust, easy-to-use hybrid implementations and compr…

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cs.CRcs.SEquant-phRecentApr 8, 2026

Broken Quantum: A Systematic Formal Verification Study of Security Vulnerabilities Across the Open-Source Quantum Computing Simulator Ecosystem

Dominik Blain

The paper presents Broken Quantum, a comprehensive formal security audit that identifies 547 security vulnerabilities across 45 open-source quantum computing simulators, revealing critical flaws in me…

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cs.CRRecentApr 17, 2026

Low-Stack HAETAE for Memory-Constrained Microcontrollers

Gustavo Banegas, Kim Youngbeom, Seo Seog Chung, Vredendaal Christine Van

The paper presents a highly optimized, low-stack implementation of the HAETAE signature scheme, reducing peak stack usage significantly to enable its use on severely memory-constrained microcontroller…

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cs.CRcs.ARcs.LGRecentMay 11, 2026

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges

Johann Knechtel, Ozgur Sinanoglu, Ramesh Karri

This review analyzes the dual impact of integrating Large Language Models (LLMs) into hardware design, detailing both their transformative potential in EDA and the critical security vulnerabilities th…

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quant-phcs.CRRecentMay 13, 2026

QCIVET: A Quantum--Classical Pipeline Integrity Framework with Contract-Based Subtype Verification and Hash-Chained Audit Traces

Esra Yeniaras, Muhammad Amin Karimov

QCIVET introduces a novel contract-based framework to ensure the integrity of hybrid quantum-classical pipelines by verifying both the structure (syntactic) and the behavior (semantic) of quantum stag…

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cs.CRRecentApr 21, 2026

A Data-Free Membership Inference Attack on Federated Learning in Hardware Assurance

Gijung Lee, Wavid Bowman, Olivia P. Dizon-Paradis, Reiner N. Dizon-Paradis +3 more

This paper presents a novel data-free Membership Inference Attack (MIA) that uses gradient inversion on Standard Cell Library Layouts (SCLLs) to reconstruct sensitive hardware images from intercepted…

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cs.CRRecentApr 2, 2026

AI-Assisted Hardware Security Verification: A Survey and AI Accelerator Case Study

Khan Thamid Hasan, Md Ajoad Hasan, Nashmin Alam, Md. Touhidul Islam +2 more

This survey reviews the integration of AI and LLMs into hardware security verification, demonstrating its potential to automate complex stages while stressing the necessity of grounding AI outputs in…

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cs.CRRecentApr 16, 2026

Emulation-based System-on-Chip Security Verification: Challenges and Opportunities

Tanvir Rahman, Shuvagata Saha, Ahmed Y. Alhurubi, Sujan Kumar Saha +2 more

This paper surveys the use of hardware emulation for security verification in System-on-Chip (SoC) design, positioning emulation as a critical, high-fidelity pre-silicon assurance technology.

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cs.ARcs.CLcs.CRRecentApr 20, 2026

Enabling AI ASICs for Zero Knowledge Proof

Jianming Tong, Jingtian Dang, Simon Langowski, Tianhao Huang +5 more

The paper introduces MORPH, a framework that reformulates Zero-Knowledge Proof (ZKP) computations to efficiently utilize AI ASICs like TPUs, achieving up to 10x higher throughput on NTT.

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cs.CRcs.DCRecentApr 17, 2026

PoSME: Proof of Sequential Memory Execution via Latency-Bound Pointer Chasing with Causal Hash Binding

David L. Condrey

The paper introduces PoSME, a cryptographic primitive that enforces strict sequential memory execution by chaining data-dependent writes, providing verifiable delay and authorship attestation.

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