This paper evaluates the security of Universal Circuits (UCs) for hardware obfuscation, demonstrating that they are effective against both oracle-guided and oracle-less attacks.

The paper proposes a hardware-efficient compound IC protection mechanism that combines lightweight cryptography with logic locking and hardware obfuscation to secure integrated circuits against variou…

This paper introduces an agentic LLM-driven framework that automates the generation of functionally correct and security-relevant hardware netlist obfuscation for protecting intellectual property.

This paper surveys the use of hardware emulation for security verification in System-on-Chip (SoC) design, positioning emulation as a critical, high-fidelity pre-silicon assurance technology.

The paper proposes 'mimetic deception,' a novel IP camouflaging technique that structurally disguises a functional IP as a different appearance IP, thereby thwarting both structural reverse engineerin…

CIPHR introduces a novel, fine-grain hardware redaction methodology inspired by cryptographic indistinguishability to protect intellectual property against structural attacks that exploit existing art…

This paper introduces a novel algorithm, CiSC, to efficiently and optimally synthesize circuit implementations of linear codes for hardware security, significantly outperforming existing state-of-the-…

This paper systematizes two decades of hardware reverse engineering research by analyzing 187 publications, identifying key technical methods and recommending improvements for reproducibility, standar…

The paper proposes a method for bit-exact verification of AI inference outputs without sacrificing performance, demonstrating that deterministic, precise re-computation is possible even across differe…

The paper analyzes the security of a partially masked hardware accelerator for Number Theoretic Transform (NTT) in PQC, demonstrating that the claimed security margins are significantly overestimated…

The paper introduces a novel hardware aging attack that exploits the commutative properties of addition to induce unbalanced stress on AI accelerator transistors, significantly degrading model accurac…

The paper introduces HarmChip, a novel benchmark to evaluate LLM vulnerability to domain-specific hardware security threats, revealing that current safety guardrails fail against semantically disguise…

This paper introduces the first explicit data obfuscation technique to protect classical sensitive values during the execution phase of quantum computation.

The paper analyzes existing hardware Trojan datasets to demonstrate that standard cell libraries can be systematically exploited to create visually undetectable, stealthy hardware Trojans, exemplified…

The paper introduces a framework, PD-FHC, that allows users to outsource Boolean computations to an untrusted cloud while guaranteeing both computational privacy and plausible deniability against coer…

The paper proposes a tamper-proofing model for self-modifying code (SMC) by leveraging external timing, concurrency, and microarchitectural state to make non-SMC reproduction detectably expensive.

The paper introduces DECIFR, a novel two-stage Membership Inference Attack (MIA) that exploits standard cell library layouts to reconstruct sensitive IC training data from intercepted federated model…

The paper introduces PVAC, a novel victim-based row counting mechanism that accurately tracks RowHammer attacks by incrementing counters on the victim row, thereby improving hammering tolerance and pe…

This review analyzes the dual impact of integrating Large Language Models (LLMs) into hardware design, detailing both their transformative potential in EDA and the critical security vulnerabilities th…

The paper proposes a novel three-layer metric framework to comprehensively evaluate quantum circuit integrity by combining structural, operational, and interaction-level analyses, demonstrating that n…