This paper presents a methodology for transitioning from Known Good Die (KGD) to Known Good Reliable Die (KGRD) screening in chiplet-based artificial intelligence systems-on-chips (SoCs) as a constrai…

This paper introduces a high-fidelity, integrated hardware-software simulator for LPDDR5X-PIM, enabling precise evaluation of system performance and energy efficiency.

The paper analyzes existing hardware Trojan datasets to demonstrate that standard cell libraries can be systematically exploited to create visually undetectable, stealthy hardware Trojans, exemplified…

This paper surveys the use of hardware emulation for security verification in System-on-Chip (SoC) design, positioning emulation as a critical, high-fidelity pre-silicon assurance technology.

The paper develops a quantitative scoring system, CRESS, to consistently and comparably rate the severity of novel hardware reverse engineering attack scenarios, proving it is more expressive than ind…

Assertain is an automated framework that uses large language models and design analysis to generate high-quality, executable security assertions for hardware designs, significantly outperforming state…

This paper proposes training a single neural network using EM traces collected from multiple probe positions to detect cryptographic leakage across a larger area of a target device, validated by cross…

This paper proposes a GPU-accelerated framework for analyzing effective resistance in 3D IC power delivery networks, achieving significant speedup with negligible error.

This paper systematizes two decades of hardware reverse engineering research by analyzing 187 publications, identifying key technical methods and recommending improvements for reproducibility, standar…

pcbGPT is a grounded system that automatically generates editable KiCad PCB schematics from natural language requirements, achieving high accuracy on complex embedded design tasks.

The paper introduces a design-oriented methodology and a closed-form macromodel to quantify how noise coupled through Through-Silicon Vias (TSVs) degrades the spectral purity of sensitive RF oscillato…

The paper proposes a visual program synthesis framework using a VLM to generate accurate training data for semiconductor inspection, mitigating the sim-to-real gap by applying input binarization to st…

VeriCWEty proposes an embedding-based framework to detect and classify common software vulnerabilities (CWEs) in Verilog RTL code at both module and line levels, achieving high detection accuracy.

This paper presents a novel approach for constructing information flow paths from RTL trace data for automated property generation and validation in hardware design.

This paper introduces PDAGENT-BENCH, a comprehensive benchmark for evaluating Large Language Models and vision-language models in the physical design stack of Very Large-Scale Integrated Circuits.

The paper systematically characterizes the fault response of the Intel NCS2 accelerator to electromagnetic fault injection, revealing a major degradation mode that is undetectable by standard inferenc…

This paper discusses the potential of Large Language Models (LLMs) in Electronic Design Automation (EDA) and reviews their applications in tasks such as circuit and testbench generation, design qualit…

The paper introduces SAMSEM, a generalized and scalable model based on SAM2, which significantly improves metal line segmentation across diverse and unseen integrated circuit (IC) samples.

The paper proposes a hardware-efficient compound IC protection mechanism that combines lightweight cryptography with logic locking and hardware obfuscation to secure integrated circuits against variou…